This thread is about the new chip we are going to build in the 180nm process.
About code compatibility with Prop1:
Hei I have a small project in the works, a verilog implementation of the P1 and I'd like some Alpha/Beta testers:
What you need:
First off, I would like to say I am sorry for asking on the parallax forum. But I don't know where I should go.
Since we have been using FDS as an example bit of code that would be affected by all of the changes, I figured I'd start tweaking it to take advantage