Today I didn't have time to work with the xilinx port. I was exploring this:
I just got 5 x P1V's running in a DE2-115. I tried to squeeze 6 in but ran out of space.
These were "standard" 80MHz 32xIO versions with
I was wondering if anyone would want to use a version of the P1 core translated from Verilog to System Verilog.
System Verilog is to Verilog
Kinda fun, several patterns and sequence questions. My score attached, so clearly it's off by 40 points or so...