I have done a lot of studies for LMM for the Prop2 before the last shuttle run. At that time there was no Hubexecute and only quad wide hub-read/write.
Hei I have a small project in the works, a verilog implementation of the P1 and I'd like some Alpha/Beta testers:
What you need:
I'm beginning to look at the feasibility of putting an ATM node in a COG. Then to put it into 2 COGS and have them communicate. Then into 7 COGS to form
This thread is about the new chip we are going to build in the 180nm process.
About code compatibility with Prop1: