Parallax Forums
  HomeLog InRegisterCommunity CalendarSearch the ForumHelp
   
Parallax Forums > Public Forums > Propeller Chip > Propeller Simulation in Verilog  Forum Quick Jump
 
New Topic Post Reply Printable Version
[ << Previous Thread | Next Thread >> ] | Show Newest Post First ]

jazzed
_oOo_(^^)_oOo_

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Jan 2008
Total Posts : 2114
  		   Posted 5/12/2009 4:27 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
Hi.

Thought I would reveal one of my Propeller projects. Verilog is a Hardware Description Language (HDL) for creating integrated circuits. I have created a single hub/cog module for simulations with Icarus Verilog. The model is not "cycle accurate" at this point (but will be) and is NOT intended for creating an image for use in an FPGA. The model does not borrow from anyone's previous work. Most of the PASM instructions have been added and many are verified to be working as expected.

What you see below is a dump of a COG simulation from a Propeller Verilog model. This is useful for connecting to other Verilog modules to verify ideas such as the Synchronous CPLD idea discussed in the 6.6MB/s thread. The dump specifically addresses the Asynchronous memory read model with data on P0..7 and address on P8..P31.

I've been working on running Chip's booter.spin code, but I've hit a wall there ... having trouble making Verilog share a pin on the EEPROM SDA line. For now I'll just give that a rest so I can focus on other things.

Using the Programming Language Interface (PLI), a model can read Propeller assembly and run the code on the COG simulation. In the future, I expect to add interfaces to "time-tick and pin data" files for describing inputs to the model so that one or more forms of a binary image can be shared ... and so that I don't have to give away my source code :). Once the full instruction set is verified, I may offer binary variations of this work on a "specified test bench."


C:\iVerilog\projects\propeller>test loadxmm

C:\iVerilog\projects\propeller>del loadxmm.binary

C:\iVerilog\projects\propeller>cat loadxmm.spin
CON
  _clkmode = xtal1 + pll16x
  _xinfreq = 5_000_000

PUB main
  cognew(@initxmm,0)

DAT
initxmm        ' initialize
               mov      dira,   mask
               mov      addr,   par
               call     #loadxmm8
               call     #loadxmm16
               call     #loadxmm32

               ' debug stuff
finish         or       dira,   #$ff
               mov      outa,   val

               ' kill cog
               cogid    cog
               cogstop  cog

loadxmm32      ' 16 total instructions for 3.3V < 50ns SRAM. Direct address/data bus
               mov      outa,   addr
               shl      outa,   #8
               add      outa,   _0x300  'add to address to fix endian order
               nop
               mov      val,    ina     'xxxxxxxxxxxxxxxxxxxxxxxxAAAAAAAA .
               sub      outa,   #$100
               ror      val,    #17 wc  'xxxxxxxxxAAAAAAAAxxxxxxxxxxxxxxx A0
               movi     val,    ina     'bBBBBBBBBAAAAAAAAxxxxxxxxxxxxxxx A0
               sub      outa,   #$100
               shr      val,    #8      '........bBBBBBBBBAAAAAAAAxxxxxxx A0
               movi     val,    ina     'cCCCCCCCCBBBBBBBBAAAAAAAAxxxxxxx A0
               sub      outa,   #$100
               shr      val,    #8      '........cCCCCCCCCBBBBBBBBAAAAAAA A0
               movi     val,    ina     'dDDDDDDDDCCCCCCCCBBBBBBBBAAAAAAA A0
               rcl      val,    #1      'DDDDDDDDCCCCCCCCBBBBBBBBAAAAAAAA A0
loadxmm32_ret  ret

loadxmm16      ' 10 total instructions for 3.3V < 50ns SRAM. Direct address/data bus
               mov      outa,   addr
               shl      outa,   #8
               add      outa,   #$100  'add to address to fix endian order
               nop
               mov      val,    ina     'xxxxxxxxxxxxxxxxxxxxxxxxAAAAAAAA .
               sub      outa,   #$100
               ror      val,    #17     'xxxxxxxxxAAAAAAAAxxxxxxxxxxxxxxx A0
               movi     val,    ina     'bBBBBBBBBAAAAAAAAxxxxxxxxxxxxxxx A0
               shr      val,    #15
loadxmm16_ret  ret


loadxmm8      '  5 total instructions for 3.3V < 50ns SRAM. Direct address/data bus
               mov      outa,   addr
               shl      outa,   #8
               nop
               mov      val,    ina     'xxxxxxxxxxxxxxxxxxxxxxxxAAAAAAAA .
loadxmm8_ret   ret

cog            long 0
_0x300         long $300
addr           long $0
mask           long $ffffff00
val            res 1

C:\iVerilog\projects\propeller>.\propellent /compile /savebinary loadxmm.spin

C:\iVerilog\projects\propeller>.\spin2pasm loadxmm.binary  1>loadxmm.txt

C:\iVerilog\projects\propeller>del tb_loadxmm

C:\iVerilog\projects\propeller>iverilog -o tb_loadxmm tb_loadxmm.v

C:\iVerilog\projects\propeller>vvp -v tb_loadxmm
Compiling VVP ...
Compile cleanup...
 ... Linking
 ... Removing symbol tables
 ...     2230 functors
                160 table
                  0 bufif
                 32 resolv
                980 variable
 ...    10338 opcodes (180224 bytes)
 ...      148 nets
 ...        9 memories
 ...        4 scopes
Running ...
VCD info: dumpfile propeller.vcd opened for output.
$readmemh(loadxmm.txt): Not enough words in the read file for requested range.
COG  0 un-reset         43  520
COG download  0 complete. PC 000 INST a0bfec2b
COG  0 PASM[000] = a0bfec2b i 28 zcri 0010 MOV      c f d 1f6 ffffff00 <- 00000000 s  02b ffffff00 DIRA     C 0 Z 0 ioa 11111111111111111111111101010101 cnt 0000016c
COG  0 PASM[001] = a0bc55f0 i 28 zcri 0010 MOV      c f d 02a 00000040 <- 00000000 s  1f0 00000040     PAR  C 0 Z 0 ioa 00000000000000000000000001010101 cnt 00000170
COG  0 PASM[002] = 5cfc4e23 i 17 zcri 0011 JMP      c f d 027 5c7c0003 <- 5c7c0000 s #023 a0bfe82a          C 0 Z 0 ioa 00000000000000000000000001010101 cnt 00000174
COG  0 PASM[023] = a0bfe82a i 28 zcri 0010 MOV      c f d 1f4 00000040 <- 00000000 s  02a 00000040 OUTA     C 0 Z 0 ioa 00000000000000000000000010101010 cnt 00000178
COG  0 PASM[024] = 2cffe808 i 0b zcri 0011 SHL      c f d 1f4 00004000 <- 00000040 s #008 0c7c5003 OUTA     C 0 Z 0 ioa 00000000000000000000000010101010 cnt 0000017c
COG  0 PASM[025] = 00000000 i 00 zcri 0000 NOP      c 0 d 000 a0bfec2b <- a0bfec2b s  000 a0bfec2b          C 0 Z 0 ioa 00000000000000000100000010101010 cnt 00000180
COG  0 PASM[026] = a0bc59f2 i 28 zcri 0010 MOV      c f d 02c ffffff55 <- xxxxxxxx s  1f2 ffffff55     INA  C 0 Z 0 ioa 00000000000000000100000001010101 cnt 00000184
COG  0 PASM[027] = 5c7c0003 i 17 zcri 0001 JMP      c f d 000 a0bfec2b <- a0bfec2b s #003 5cfc4419          C 0 Z 0 ioa 00000000000000000100000001010101 cnt 00000188
COG  0 PASM[003] = 5cfc4419 i 17 zcri 0011 JMP      c f d 022 5c7c0004 <- 5c7c0000 s #019 a0bfe82a          C 0 Z 0 ioa 00000000000000000100000001010101 cnt 0000018c
COG  0 PASM[019] = a0bfe82a i 28 zcri 0010 MOV      c f d 1f4 00000040 <- 00004000 s  02a 00000040 OUTA     C 0 Z 0 ioa 00000000000000000100000010101010 cnt 00000190
COG  0 PASM[01a] = 2cffe808 i 0b zcri 0011 SHL      c f d 1f4 00004000 <- 00000040 s #008 0c7c5003 OUTA     C 0 Z 0 ioa 00000000000000000000000010101010 cnt 00000194
COG  0 PASM[01b] = 80ffe900 i 20 zcri 0011 ADD      c f d 1f4 00004100 <- 00004000 s #100 xxxxxxxx OUTA     C 0 Z 0 ioa 00000000000000000100000010101010 cnt 00000198
COG  0 PASM[01c] = 00000000 i 00 zcri 0000 NOP      c 0 d 000 a0bfec2b <- a0bfec2b s  000 a0bfec2b          C 0 Z 0 ioa 00000000000000000100000101010101 cnt 0000019c
COG  0 PASM[01d] = a0bc59f2 i 28 zcri 0010 MOV      c f d 02c ffffff55 <- ffffff55 s  1f2 ffffff55     INA  C 0 Z 0 ioa 00000000000000000100000101010101 cnt 000001a0
COG  0 PASM[01e] = 84ffe900 i 21 zcri 0011 SUB      c f d 1f4 00004000 <- 00004100 s #100 xxxxxxxx OUTA     C 0 Z 0 ioa 00000000000000000100000101010101 cnt 000001a4
COG  0 PASM[01f] = 20fc5811 i 08 zcri 0011 ROR      c f d 02c ffaaffff <- ffffff55 s #011 84ffe900          C 0 Z 0 ioa 00000000000000000100000010101010 cnt 000001a8
COG  0 PASM[020] = 58bc59f2 i 16 zcri 0010 MOVI     c f d 02c 552affff <- ffaaffff s  1f2 000000aa     INA  C 0 Z 0 ioa 00000000000000000100000010101010 cnt 000001ac
COG  0 PASM[021] = 28fc580f i 0a zcri 0011 SHR      c f d 02c 0000aa55 <- 552affff s #00f 21fc5811          C 0 Z 0 ioa 00000000000000000100000010101010 cnt 000001b0
COG  0 PASM[022] = 5c7c0004 i 17 zcri 0001 JMP      c f d 000 a0bfec2b <- a0bfec2b s #004 5cfc3009          C 0 Z 0 ioa 00000000000000000100000001010101 cnt 000001b4
COG  0 PASM[004] = 5cfc3009 i 17 zcri 0011 JMP      c f d 018 5c7c0005 <- 5c7c0000 s #009 a0bfe82a          C 0 Z 0 ioa 00000000000000000100000001010101 cnt 000001b8
COG  0 PASM[009] = a0bfe82a i 28 zcri 0010 MOV      c f d 1f4 00000040 <- 00004000 s  02a 00000040 OUTA     C 0 Z 0 ioa 00000000000000000100000001010101 cnt 000001bc
COG  0 PASM[00a] = 2cffe808 i 0b zcri 0011 SHL      c f d 1f4 00004000 <- 00000040 s #008 0c7c5003 OUTA     C 0 Z 0 ioa 00000000000000000000000010101010 cnt 000001c0
COG  0 PASM[00b] = 80bfe829 i 20 zcri 0010 ADD      c f d 1f4 00004300 <- 00004000 s  029 00000300 OUTA     C 0 Z 0 ioa 00000000000000000100000010101010 cnt 000001c4
COG  0 PASM[00c] = 00000000 i 00 zcri 0000 NOP      c 0 d 000 a0bfec2b <- a0bfec2b s  000 a0bfec2b          C 0 Z 0 ioa 00000000000000000100001110101010 cnt 000001c8
COG  0 PASM[00d] = a0bc59f2 i 28 zcri 0010 MOV      c f d 02c ffffff55 <- 0000aa55 s  1f2 ffffff55     INA  C 0 Z 0 ioa 00000000000000000100001101010101 cnt 000001cc
COG  0 PASM[00e] = 84ffe900 i 21 zcri 0011 SUB      c f d 1f4 00004200 <- 00004300 s #100 xxxxxxxx OUTA     C 0 Z 0 ioa 00000000000000000100001101010101 cnt 000001d0
COG  0 PASM[00f] = 21fc5811 i 08 zcri 0111 ROR      c f d 02c ffaaffff <- ffffff55 s #011 84ffe900          C 1 Z 0 ioa 00000000000000000100001001010101 cnt 000001d4
COG  0 PASM[010] = 58bc59f2 i 16 zcri 0010 MOVI     c f d 02c 552affff <- ffaaffff s  1f2 000000aa     INA  C 1 Z 0 ioa 00000000000000000100001010101010 cnt 000001d8
COG  0 PASM[011] = 84ffe900 i 21 zcri 0011 SUB      c f d 1f4 00004100 <- 00004200 s #100 xxxxxxxx OUTA     C 1 Z 0 ioa 00000000000000000100001010101010 cnt 000001dc
COG  0 PASM[012] = 28fc5808 i 0a zcri 0011 SHR      c f d 02c 00552aff <- 552affff s #008 0c7c5003          C 1 Z 0 ioa 00000000000000000100000110101010 cnt 000001e0
COG  0 PASM[013] = 58bc59f2 i 16 zcri 0010 MOVI     c f d 02c aad52aff <- 00552aff s  1f2 ffffff55     INA  C 1 Z 0 ioa 00000000000000000100000101010101 cnt 000001e4
COG  0 PASM[014] = 84ffe900 i 21 zcri 0011 SUB      c f d 1f4 00004000 <- 00004100 s #100 xxxxxxxx OUTA     C 1 Z 0 ioa 00000000000000000100000101010101 cnt 000001e8
COG  0 PASM[015] = 28fc5808 i 0a zcri 0011 SHR      c f d 02c 00aad52a <- aad52aff s #008 0c7c5003          C 1 Z 0 ioa 00000000000000000100000001010101 cnt 000001ec
COG  0 PASM[016] = 58bc59f2 i 16 zcri 0010 MOVI     c f d 02c 552ad52a <- 00aad52a s  1f2 000000aa     INA  C 1 Z 0 ioa 00000000000000000100000010101010 cnt 000001f0
COG  0 PASM[017] = 34fc5801 i 0d zcri 0011 RCL      c f d 02c aa55aa55 <- 552ad52a s #001 a0bc55f0          C 1 Z 0 ioa 00000000000000000100000010101010 cnt 000001f4
COG  0 PASM[018] = 5c7c0005 i 17 zcri 0001 JMP      c f d 000 a0bfec2b <- a0bfec2b s #005 68ffecff          C 1 Z 0 ioa 00000000000000000100000010101010 cnt 000001f8
COG  0 PASM[005] = 68ffecff i 1a zcri 0011 OR       c f d 1f6 ffffffff <- ffffff00 s #0ff xxxxxxxx DIRA     C 1 Z 0 ioa 00000000000000000100000001010101 cnt 000001fc
COG  0 PASM[006] = a0bfe82c i 28 zcri 0010 MOV      c f d 1f4 aa55aa55 <- 00004000 s  02c aa55aa55 OUTA     C 1 Z 0 ioa 00000000000000000100000000000000 cnt 00000200
COG  0 PASM[007] = 0cfc5001 i 03 zcri 0011 HUBOP    c f d 028 00000000 <- 00000000 s #001 a0bc55f0          C 1 Z 0 ioa 10101010010101011010101001010101 cnt 00000204
COG  0 PASM[008] = 0c7c5003 i 03 zcri 0001 HUBOP    c f d 028 00000000 <- 00000000 s #003 5cfc4419          C 1 Z 0 ioa 10101010010101011010101001010101 cnt 00000208
Event counts: (event pool = 1364)
       20290 thread schedule events
        9833 propagation events
       29326 assign events
      440384 other events
"Use: gtkwave propeller.vcd"

C:\iVerilog\projects\propeller>

--Steve
 
Back to Top
 

Rayman
Registered Member

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Jul 2007
Total Posts : 2408
  		   Posted 5/12/2009 4:41 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
Sounds like fun! I was about to dive into FPGA stuff before I stumbled across the Propeller... It'd be nice to make custom Props though. Can you make one with 64 I/O pins?

My Prop Info&Apps:  http://www.rayslogic.com/propeller/propeller.htm

Back to Top
 

jazzed
_oOo_(^^)_oOo_

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Jan 2008
Total Posts : 2114
  		   Posted 5/12/2009 5:09 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
Rayman.
I can make simulations with 64 I/O and MUL instructions too. But like I said sort of, my plan is to "make simulations, not chips."

--Steve
 
Back to Top
 

localroger
Registered Member



Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Mar 2009
Total Posts : 417
  		   Posted 5/12/2009 5:12 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
I think the FPGA would have trouble with things like the counters and PLL's. And aren't most FPGA's a lot more expensive than the prop now?
Back to Top
 

jazzed
_oOo_(^^)_oOo_

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Jan 2008
Total Posts : 2114
  		   Posted 5/12/2009 5:52 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
I know that PLL's have been done on VirtexII. I have not implemented counters or WAITVID. That will be a PITA; possible but a PITA.
No way that a 32 I/O FPGA Propeller could compete price-wise with P8X32A.

--Steve
 
Back to Top
 

Cluso99
We live onboard



Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Apr 2008
Total Posts : 2276
  		   Posted 5/12/2009 7:35 PM (GMT -8)    Quote This PostAlert An Admin About This Post.

Great work Steve roll

I really like the idea of being able to simulate the hardware as that would be the basis of a good debugger as you have no doubt found.

As you and some others know, I was playing with a cog emulation in an FPGA using Verilog. I am not the only one. I am (was, because I stopped at Xmas to design some prop hardware) using a Xilinx Spartan-3A (XC3S400A).

Just some info: The FPGA's will use a lot more power and cost more than a real prop.  While it may be possible to fit a prop in my FPGA, the hub memory will definately not fit inside. There are much larger versions but they are all BGA with 400+ pins and $$$.

Links to other interesting threads:
Back to Top
 

jazzed
_oOo_(^^)_oOo_

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Jan 2008
Total Posts : 2114
  		   Posted 11/4/2009 10:37 AM (GMT -8)    Quote This PostAlert An Admin About This Post.
I'm reviving this project. The goal has changed:

    Create a functional FPGA with external HUB RAM that will be finished before Propeller II.

A Propeller PASM compatible P8X32A/B FPGA core using 32MB external HUB RAM directly accessible to COGs
in the natural way (directly accessible to LMM via special instructions) and running on Spartan 3E.
I will abandon the effort only when Propeller II is ready for sale, when my FPGA board functions perfectly
IMHO, I receive a "cease and desist letter" or post from Parallax, or stop for significant personal reasons.

The target hardware will initially be the Diligent Spartan 3E S3E1600 FPGA Board. ... This board has 32MB
Micron DDR 5ns memory, 16MB Intel StrataFlash Flash, Xilinx Program Flash, 16MB Serial Flash, DB15HD VGA
PS/2 keyboard, 2 DB9 RS-232 connectors, RJ-45 Ethernet, 16-pin header for optional LCD modules, I/O
connectors, and USB for programing.

The Diligent 1600K board/PS is about $230, 500K board/PS is about $150 (international distribution available).

It is unclear how many COGs could be put into the 1600K device with on-board FPGA COG RAM and external
HUB RAM, but more than 8 is likely. One of my design goals is to allow any number of COGs (8 more or
less) that will fit into a given device. It is unclear if 8 COGs will fit into the Spartan 3E-500K.

I am committed to this since I'm sick of waiting for Propeller II, but I do not recommend anyone without sufficient
knowledge in purchasing hardware until there is reasonable progress. Others who feel qualified are welcome to
join me in development.
Back to Top
 

Ale
Registered Member



Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined May 2007
Total Posts : 1267
  		   Posted 11/4/2009 10:52 AM (GMT -8)    Quote This PostAlert An Admin About This Post.
jazzed, I'd like to know how much logic is needed for at least 1 COG. I know that 1.6M gates is quite a bit but do you have any estimation ?

I'd love to join the development but I am just beginning with Verilog, I'm still thinking about gates and FFs instead of behaviour :-(. I just today got the CPLD code for memory control working with incrementing pointer. I have now to add a second pointer and well, it is sort of ready. Sorry for hijiking your thread.
Great stuff !!

Visit some of my articles at Propeller Wiki:
MATH on the propeller propeller.wikispaces.com/MATH
pPropQL: propeller.wikispaces.com/pPropQL
pPropQL020: propeller.wikispaces.com/pPropQL020
OMU for the pPropQL/020 propeller.wikispaces.com/OMU

Back to Top
 

Cluso99
We live onboard



Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Apr 2008
Total Posts : 2276
  		   Posted 11/4/2009 12:35 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
I have done the instruction decoding, cog memory fetching and writing using dual access, flag testing and setting. I abandoned at the point of implementing the barrel shifter. I was working on a 1-4 cycle instruction with 2 pipes to give 1-3 cycles effective.

Not sure if I am willing to disclose the code - would probably talk to Parallax first. It is in verilog for a Spartan 3A 200 $50 Avnet pcb.

Links to other interesting threads:
Back to Top
 

jazzed
_oOo_(^^)_oOo_

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Jan 2008
Total Posts : 2114
  		   Posted 11/4/2009 1:49 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
@Ale, I don't know yet how big one COG will be. I'm working with the verilog from my
simulation model now to make it synthesizable ... could be a while before that's ready.

As I said in so many words in another thread:
I believe it's better to start too big than to start too small.

@Cluso99, I've already stated my intentions.
If Parallax wants me to stop I will, but I am quite sick of waiting for Propeller II.

It's either this or abandon Propeller completely for me.
I'm sure some folks here would like to see me abandon it and this forum :)
Back to Top
 

nutson
Registered Member

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined May 2006
Total Posts : 107
  		   Posted 11/4/2009 2:14 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
You are a brave man. Jazzed. I got my Verilog soft-COG about half way, stable executing a substantial subset of ASM instructions at 150MHz/50MIPS. I got stuck at interfacing this CPU to the DE-1 board 256K16 memory, doubling as a 1024X512X8 bit XGA graphics memory (65MHz pixel frequency).  This required a serious asynchronous bus design with wait states and the lot, more than I could handle (see the simple CPU interface definition I started with).  With the board you have chosen I would go for a synchronous design with 4 COGS and 64KByte of hub memory, you have exectly 72KByte on chip fast dual port memory. Using the 16 bit DDR DRAM as hub memory seems a timing PITA to me.  
 
Regards
 
 
http://forums.parallax.com/forums/default.aspx?f=25&p=1&m=305800
Image Attachment :
Image Preview
soft-COG-interface.JPG   85KB (image/pjpeg)
This image has been viewed 21 time(s).
Back to Top
 

Ron Sutcliffe
Registered Member

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Oct 2007
Total Posts : 209
  		   Posted 11/4/2009 4:37 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
@jazzed
Well, I can certainly understand your frustration.

Trying to do anything with C on Propeller, other than a perhaps a few party tricks, is like trying to lubricate a bicycle at a Well Head in Texas.
The only reason C developer would choose Prop is take advantage of the video services availble in each cog.

For what its worth, I think it would be better to develop standalone hardware optimized around large memory, but supporting access to Props Video and the PPL services. In other words leave the Video generator stuff off the hardware (AKA Prop1 with 64 pins less Video and PLL) 

I don’t image you are alone doing what you are doing, so there would be little point in Parallax asking you to stop, but may you will have to consider continuing a thread like this at another venue. If you do let me know :)

I can’t believe anyone would want to see you leave Prop land, your contributions would be surely missed.

Ron

Post Edited (Ron Sutcliffe) : 11/5/2009 6:44:33 AM GMT

Back to Top
 

Cluso99
We live onboard



Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Apr 2008
Total Posts : 2276
  		   Posted 11/4/2009 7:46 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
Jazzed: I don't think anyone would like to see you leave the prop.

I understand you want the Prop II. So do we all, but we are using what is available.

From the work I did, I think you will find the counters the most complex part of the design. However, I guess you can put just the blocks in the FPGA for 1 VGA, 2 UARTs, etc as they are all available as free IPs.

Links to other interesting threads:
Back to Top
 

Nick Mueller
Registered Member

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Apr 2007
Total Posts : 694
  		   Posted 11/4/2009 10:20 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
WOW! You are nuts!

The only contribution I can make is to wish you the very best for this project.

Imagine what this means: A Prop in an FPGA, you could add clue-logic inside of the "Prop" and thus reduce size. Maybe even use some spare instructions for special purposes, add hardware I2C & SPI, have "unlimited" RAM, maybe even map regions of external RAM into HUB-RAM, maybe have more COGs, ...
The possibilities seem to be endless!

Chapeau!
Nick

Never use force, just go for a bigger hammer!

The DIY Digital-Readout for mills, lathes etc.:
YADRO

Back to Top
 

FredBlais
Registered Member

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Jul 2008
Total Posts : 53
  		   Posted 11/5/2009 8:32 AM (GMT -8)    Quote This PostAlert An Admin About This Post.
If I understand... we could run binary of Spin/asm source code generated from the prop tool in a soft-prop and have the choice of how many cogs or RAM we want? Maybe you'll want to look at recents CoWare tools and LISA.
 
LISA is...
a Language targeting the description of Instruction Set Architecture. The aim is to capture all the information required to generate software tools (compiler, assembler, Instruction Set Simulator, ...) and implementation hardware (in VHDL or Verilog) of a given processor core.
At the lab I'm working, some PhD people are using these tools to create soft-processor core architecture perfectly suited to accelerate motor control algorithms like vectored motor control. It is said that using these tools save months/years of development to people that want to make a core from scratch.
Back to Top
 

jazzed
_oOo_(^^)_oOo_

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Jan 2008
Total Posts : 2114
  		   Posted 11/5/2009 10:34 AM (GMT -8)    Quote This PostAlert An Admin About This Post.
FredBlais said...
If I understand... we could run binary of Spin/asm source code generated from the prop tool in a soft-prop and have the choice of how many cogs or RAM we want?

That is an attractive feature assuming synthesizable compatible verilog exists :)
The tool you mentioned is attractive.

My laptop got a Windows update last night. I'm having huge problems with that.
Everything is on hold now. Microsoft really screwed me this time. I'm sure they
will find a way to blame me for the problem ... mad

(Posting from reliable Linux today).
Back to Top
 

Ale
Registered Member



Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined May 2007
Total Posts : 1267
  		   Posted 11/5/2009 10:40 AM (GMT -8)    Quote This PostAlert An Admin About This Post.
The EULA says that the software is not fit for any purpose or something like that....

Visit some of my articles at Propeller Wiki:
MATH on the propeller propeller.wikispaces.com/MATH
pPropQL: propeller.wikispaces.com/pPropQL
pPropQL020: propeller.wikispaces.com/pPropQL020
OMU for the pPropQL/020 propeller.wikispaces.com/OMU

Back to Top
 

FredBlais
Registered Member

Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Jul 2008
Total Posts : 53
  		   Posted 11/5/2009 11:14 AM (GMT -8)    Quote This PostAlert An Admin About This Post.
jazzed said...
The tool you mentioned is attractive.
 
Back to Top
 

Cluso99
We live onboard



Email Address Not AvailablePersonal Homepage Not AvailablePrivate Messaging Not AvailableAIM Not AvailableICQ Not AvailableY! Not AvailableMSN Not Available
Date Joined Apr 2008
Total Posts : 2276
  		   Posted 11/5/2009 5:49 PM (GMT -8)    Quote This PostAlert An Admin About This Post.
I control my windoze updates for that very reason. I only do updates when I don't have something critical happening - been there before. Once with a virus program quarantining wondoze forcing a complete reformat :(

Still, it is better than years ago when reformatting every 3 months was mandatory for windoze developers.

Links to other interesting threads:
Back to Top
 
[ << Previous Thread | Next Thread >> ]
New Topic Post Reply Printable Version
 
Forum Information
Currently it is Friday, November 20, 2009 10:58 PM (GMT -8)
There are a total of 393,737 posts in 55,521 threads.
In the last 3 days there were 82 new threads and 702 reply posts. View Active Threads
Who's Online
This forum has 17687 registered members. Please welcome our newest member, mark09.
56 Guest(s), 6 Registered Member(s) are currently online.  Details
Peter Verkaik, BradC, Harley, Chris Savage (Parallax), Rich_W8VK, potatohead
Forum powered by dotNetBB v2.42EC SP2.02
dotNetBB © 2000-2009

Need Support? | Forum Help Manual