ÿþ{{ ************************************************ * Propeller SPI Engine ... Spin Version v1.1 * * Author: Beau Schwabe * * Copyright (c) 2009 Parallax * * See end of file for terms of use. * ************************************************ Revision History: V1.0 - original program V1.1 - modified by Pat Daderko (DogP) to allow SPI Master or Slave (not thoroughly tested) }} CON #0,MSBPRE,LSBPRE,MSBPOST,LSBPOST '' Used for SHIFTIN routines ''  ð  ð  ð  ð '' =0 =1 =2 =3 '' '' MSBPRE - Most Significant Bit first ; data is valid before the clock '' LSBPRE - Least Significant Bit first ; data is valid before the clock '' MSBPOST - Most Significant Bit first ; data is valid after the clock '' LSBPOST - Least Significant Bit first ; data is valid after the clock #4,LSBFIRST,MSBFIRST '' Used for SHIFTOUT routines ''  ð  ð '' =4 =5 '' '' LSBFIRST - Least Significant Bit first ; data is valid after the clock '' MSBFIRST - Most Significant Bit first ; data is valid after the clock MASTER=0 SLAVE=1 VAR long ClockDelay,ClockState,MasterSlave PUB start(_ClockDelay, _ClockState) ClockState := _ClockState ClockDelay := ((clkfreq / 100000 * _ClockDelay) - 4296) #> 381 MasterSlave := MASTER 'default to Master for backwards compatibility PUB setMasterSlave(_MasterSlave) MasterSlave := _MasterSlave PUB SHIFTOUT(Dpin, Cpin, Mode, Bits, Value) dira[Dpin]~~ ' make Data pin output if MasterSlave == MASTER outa[Cpin] := ClockState ' set initial clock state dira[Cpin]~~ ' make Clock pin output else dira[Cpin]~ ' make Clock pin input if Mode == 4 'LSBFIRST Value <-= 1 ' pre-align lsb repeat Bits outa[Dpin] := (Value ->= 1) & 1 ' output data bit PostClock(Cpin) if Mode == 5 'MSBFIRST Value <<= (32 - Bits) ' pre-align msb repeat Bits outa[Dpin] := (Value <-= 1) & 1 ' output data bit PostClock(Cpin) PUB SHIFTIN(Dpin, Cpin, Mode, Bits)|Value dira[Dpin]~ ' make Data pin input if MasterSlave == MASTER outa[Cpin] := ClockState ' set initial clock state dira[Cpin]~~ ' make cpin output else dira[Cpin]~ ' make Clock pin input Value~ ' clear output if Mode == 0 'MSBPRE repeat Bits value := (Value << 1) | ina[Dpin] PostClock(Cpin) if Mode == 1 'LSBPRE repeat Bits +1 Value := (Value >> 1) | (ina[Dpin] << 31) PostClock(Cpin) value >>= (32 - Bits) if Mode == 2 'MSBPOST repeat Bits PreClock(Cpin) Value := (Value << 1) | ina[Dpin] if Mode == 3 'LSBPOST repeat Bits + 1 PreClock(Cpin) Value := (Value >> 1) | (ina[Dpin] << 31) Value >>= (32 - Bits) return Value PUB PostClock(_Cpin) | clkstate if MasterSlave == MASTER waitcnt(cnt+ClockDelay) !outa[_Cpin] waitcnt(cnt+ClockDelay) !outa[_Cpin] else if ClockState == 0 waitpne(|<_Cpin, |<_Cpin, 0) 'wait for low waitpeq(|<_Cpin, |<_Cpin, 0) 'wait for rising edge else waitpeq(|<_Cpin, |<_Cpin, 0) 'wait for high waitpne(|<_Cpin, |<_Cpin, 0) 'wait for falling edge PUB PreClock(_Cpin) | clkstate if MasterSlave == MASTER !outa[_Cpin] waitcnt(cnt+ClockDelay) !outa[_Cpin] waitcnt(cnt+ClockDelay) else if ClockState == 0 waitpne(|<_Cpin, |<_Cpin, 0) 'wait for low waitpeq(|<_Cpin, |<_Cpin, 0) 'wait for rising edge else waitpeq(|<_Cpin, |<_Cpin, 0) 'wait for high waitpne(|<_Cpin, |<_Cpin, 0) 'wait for falling edge DAT {{ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % TERMS OF USE: MIT License % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%$% %Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation % %files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, % %modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software% %is furnished to do so, subject to the following conditions: % % % %The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.% % % %THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE % %WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR % %COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, % %ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% }}