'' ctr test


CON

  _clkmode = xtal1 + pll16x                             ' use crystal x 16
  _xinfreq = 5_000_000
  

OBJ

  lcd   : "debug_lcd"


PUB main | ctr, hz, t

  if lcd.start(0, 19_200, 4)
    lcd.cursor(0)
    lcd.cls
    lcd.backlight(1)

    ctra := constant(%00100 << 26) | 16                 ' single-ended nco mode on A16
    frqa := fraction(100, clkfreq, 1)                   ' set for 100 Hz
    dira[16]~~                                          ' make a16 an output

    ctrb := constant(%01010 << 26) | 16                 ' posedge detection on A16 
    frqb := 1                                           ' one count per edge

    t := cnt                                            ' sync with system counter
    repeat
      phsb~                                             ' clear phase register
      waitcnt(t += clkfreq)                             ' wait one second
      lcd.home
      lcd.decf(phsb, 5)                                 ' display phase count (hz)
      lcd.str(string(" Hz"))
      
      
PRI fraction(a, b, shift) : f

  if shift > 0                                          ' if shift, pre-shift a or b left
    a <<= shift                                         ' to maintain significant bits while 
  if shift < 0                                          ' insuring proper result
    b <<= -shift
 
  repeat 32                                             ' perform long division of a/b
    f <<= 1
    if a => b
      a -= b
      f++           
    a <<= 1    
    
   