{ GETRND test Dip settings for P2_ES board FLASH on. Set P59 pulldown for Fast SPI boot } con crystal = 20_000_000 dv = 40 mlt = 360 '180 Mhz clk = 1 << 24 | (dv-1) << 18 | (mlt-1) << 8 sys_clk = crystal / dv * mlt #58,spi_do,spi_di,spi_clk,spi_cs write_enable = $06 block_erase_64k = $D8 read_status = 5 enable_reset = $66 device_reset = $99 read_data = 3 page_program = 2 baudrate = 115200 clocksperbit = float(sys_clk) / float(baudrate) nco = round(clocksperbit * 65536.0) & $FFFFFC00 rx_pin = 63 tx_pin = 62 '============================================================================================== dat org hubset ##clk | %1111_10_00 'enable crystal+PLL, stay in 20MHz+ mode waitx ##20_000_000/100 'wait ~10ms for crystal+PLL to stabilize hubset ##clk | %1111_10_11 'now switch to PLL running at 180 MHz drvh #spi_cs drvl #spi_clk drvl #spi_di 'compute checksum for SPI flash boot call #checksum subr pa,##$706F7250 'Prop' wrlong pa,ptra[-1] 'reset flash callpa #enable_reset,#send_command callpa #device_reset,#send_command 'erase flash erase_stage1 mov addr,#0 call #erase_64k 'copy stage1 loader call #copy_stage1 rep #3,#0 drvnot #56 'flash programming complete (blink led waitx ##sys_clk/2 jmp #$ erase_64k callpa #write_enable,#send_command outl #spi_cs mov data,#block_erase_64k call #send_byte call #send_addr24 outh #spi_cs call #busy ret copy_stage1 mov pages,#4 mov addr,#0 loc ptra,#@stage1 .loop2 callpa #write_enable,#send_command mov byte_count,#256 outl #spi_cs mov data,#page_program call #send_byte call #send_addr24 .loop rdbyte data,ptra++ call #send_byte djnz byte_count,#.loop outh #spi_cs call #busy add addr,#256 djnz pages,#.loop2 ret send_command drvl #spi_cs mov data,pa call #send_byte drvh #spi_cs ret read_byte mov count,#8 .loop call #clock testp #spi_do wc rcl val,#1 djnz count,#.loop ret send_addr24 getbyte data,addr,#2 call #send_byte getbyte data,addr,#1 call #send_byte getbyte data,addr,#0 call #send_byte ret send_byte mov count,#8 .loop testb data,#7 wc drvc #spi_di shl data,#1 call #clock djnz count,#.loop ret clock drvh #spi_clk drvl #spi_clk ret busy outl #spi_cs mov data,#read_status call #send_byte call #read_byte outh #spi_cs testb val,#0 wc 'write in progress if_c jmp #busy ret checksum loc ptra,#@stage1 mov pa,#0 rep @loop,#256 rdlong pb,ptra++ add pa,pb loop ret blocks long 0 count long 0 addr long 0 data long 0 pages long 0 xx long 0 byte_count long 0 val long 0 '============================================================================================== orgh $400 org stage1 getrnd value hubset ##clk | %1111_10_00 'enable crystal+PLL, stay in 20MHz+ mode waitx ##20_000_000/100 'wait ~10ms for crystal+PLL to stabilize hubset ##clk | %1111_10_11 'now switch to PLL running at 180 MHz wrpin #%1_11110_0,#tx_pin wxpin ##nco | 7,#tx_pin dirh #tx_pin waitx ##sys_clk * 20 'allow time for teerminal start call #send_hex8 'show result call #newline jmp #$ newline mov pa,#13 send_char rdpin pb,#tx_pin wc if_c jmp #send_char wypin pa,#tx_pin ret wcz send_hex8 mov countx,#8 .loop getnib pa,value,#7 cmp pa,#9 wcz if_a add pa,#"A"-10 if_be add pa,#"0" call #send_char rol value,#4 djnz countx,#.loop ret value res 1 countx res 1 orgf $100