The Propeller 2 is a microcontroller containing 1, 2, 4, 8, or 16 identical 32-bit processors called “cogs”, which connect to a common “hub”. The hub provides a shared RAM, a CORDIC math solver, and housekeeping facilities. The architecture supports up to 64 smart I/O pins, each capable of many autonomous analog and digital functions. 
Each cog has: 
		-  Access to all I/O pins, plus four fast DAC output channels 

		-  512 longs of dual-port register RAM for code and fast variables 

		-  512 longs of dual-port lookup RAM for code, streamer lookup, and variables 

		-  Ability to execute code directly from register RAM, lookup RAM, and hub RAM 

		-  ~350 unique instructions for math, logic, timing, and control operations 

		-  2-clock execution for all math and logic instructions, including 16 x 16 multiply 

		-  6-clock custom-bytecode executor for interpreted languages 

		-  Ability to stream hub RAM and/or lookup RAM to DACs and pins, also pins to hub RAM 

		-  Live colorspace conversion using a 3 x 3 matrix with 8-bit signed/unsigned coefficients 

		-  Pixel blending instructions for 8:8:8:8 data 

		-  16 unique event trackers that can be polled and waited upon 

		-  3 prioritized interrupts that trigger on selectable events 

		-  Hidden debug interrupt for single-stepping, breakpoint, and polling 

The hub provides the cogs with: 
		-  Up to 1MB of contiguous RAM in a 20-bit address space 
		-  32-bits-per-clock sequential read/write for all cogs, simultaneously 

		-  readable and writable as bytes, words, or longs 

		-  last 16KB of RAM also appears at end of 1MB map and is write-protectable 

		-  32-bit, pipelined CORDIC solver with scale-factor correction 
		-  32-bit x 32-bit unsigned multiply with 64-bit result 

		-  64-bit / 32-bit unsigned divide with 32-bit quotient and 32-bit remainder 

		-  64-bit → 32-bit square root 

		-  Rotate (X32,Y32) by Theta32 → (X32,Y32) 

		-  (Rho32,Theta32) → (X32,Y32) polar-to-cartesian 

		-  (X32,Y32) → (Rho32,Theta32) cartesian-to-polar 

		-  32 → 5.27 unsigned-to-logarithm 

		-  5.27 → 32 logarithm-to-unsigned 

		-  Cogs can start CORDIC operations every 1/2/4/8/16 clocks and get results 55 clocks later 

		-  16 semaphore bits with atomic read-modify-write operations 

		-  32-bit free-running counter, increments every clock, cleared on reset 

		-  High-quality PRNG (Xoroshiro128**), updates every clock, unique data to each cog and pin 

		-  Mechanisms for starting, polling, and stopping cogs 

		-  16KB boot ROM 
		-  Loads into last 16KB of hub RAM on boot-up 

		-  SPI loader for automatic startup from 8-pin flash or SD card 

		-  Serial loader for startup from host 

Each smart I/O pin has the following functions: 
		-  8-bit, 120-ohm (3ns) and 1k-ohm DACs with 16-bit oversampling, noise, and high/low digital modes 

		-  Delta-sigma ADC with 5 ranges, 2 sources, and VIO/GIO calibration 

		-  Logic, Schmitt, pin-to-pin-comparator, and 8-bit-level-comparator input modes 

		-  2/3/5/8-bit-unanimous input filtering with selectable sample rate 

		-  Incorporation of inputs from relative pins, -3 to +3 

		-  Negative or positive local feedback, with or without clocking 

		-  Separate drive modes for high and low output: logic/1.5k/15k/150k/1mA/100uA/10uA/float 

		-  Programmable 32-bit clock output, transition output, NCO/duty output 

		-  Triangle/sawtooth/SMPS PWM output, 16-bit frame with 16-bit prescaler 

		-  Quadrature decoding with 32-bit counter, both position and velocity modes 

		-  16 different 32-bit measurements involving one or two signals 

		-  USB full-speed and low-speed (via odd/even pin pairs) 

		-  Synchronous serial transmit and receive, 1 to 32 bits 

		-  Asynchronous serial transmit and receive, 1 to 32 bits, up to clock/3 
Six different clock modes, all under software control with glitch-free switching between sources: 

		-  Internal 20MHz+ RC oscillator, nominally 24MHz, used as initial clock source 

		-  Crystal oscillator with internal loading caps for 7.5pF/15pF crystals, can feed PLL 

		-  Clock input, can feed PLL 

		-  Fractional PLL with 1..64 crystal divider --> 1..1024 VCO multiplier --> optional (1..15)*2 VCO post-divider 

		-  Internal ~20KHz RC oscillator for low-power operation (100uA) 

		-  Clock can be stopped for lowest power until reset (34uA)