fl { MCP3204/MCP3208(12bit serial A/D converter) PropForth5.5 2013/04/07 23:17:32 MCP3204 --------- --|CH0 Vdd|-- +5V --|CH1 Vref|-- +5V --|CH2 AGND|-- GND --|CH3 CLK|-- P2 --|NC Dout|-- 2.2kohm --| --|NC Din|-- ----------|-- P1 GND--|DGND _CS|-- P0 --------- } lockdict create a_mcp320* forthentry $C_a_lxasm w, h13E h113 1- tuck - h9 lshift or here W@ alignl h10 lshift or l, z2WyPW1 l, zfiPZB l, z20yPO1 l, z2WyPb1 l, zfiPeB l, z20yPO1 l, z2WyPj1 l, zfiPmB l, z20yPO1 l, z1SyLI[ l, z2WiPuB l, zfyPr3 l, z1SyLI[ l, z20iPuB l, z1byPrG l, z2WyPO0 l, zfyPrR l, z2WyQ05 l, z1[ixZC l, zgyPr1 l, z1bfxZD l, z1Syafr l, z1[ixZD l, z3[yQ4] l, z1[ixmD l, z1Syafr l, z2WyQ0D l, zfyPO1 l, z1Syafr l, 0 l, z1YFPil l, z20oPO1 l, z3[yQ4h l, zbyPO1 l, z1bixZC l, z1bixmD l, z1SV01X l, z1bixZE l, z2WiQFk l, z20yQ8G l, z3ryQ80 l, z1[ixZE l, z1SV000 l, freedict 0 wconstant _cs 1 wconstant _dpin 2 wconstant _clk \ Initialize MCP320* \ ( -- ) : init_mcp _cs 3 0 do dup pinout 1+ loop drop _cs pinhi ; { \ ( n1 n2 n3 -- n4 ) n1:channel number n2:single[1]/differential[0] n3:top pin number n4:result \ $C_treg1 -- _csm \ $C_treg2 -- _dpinm \ $C_treg3 -- _clkm \ $C_treg4 -- control data \ $C_treg5 -- loop counter \ $C_treg6 -- delay counter \ $C_stTOS -- result fl build_BootOpt :rasm \ Get _csm mov $C_treg1 , # 1 shl $C_treg1 , $C_stTOS add $C_stTOS , # 1 \ Get _dpinm mov $C_treg2 , # 1 shl $C_treg2 , $C_stTOS add $C_stTOS , # 1 \ Get _clkm mov $C_treg3 , # 1 shl $C_treg3 , $C_stTOS add $C_stTOS , # 1 spop \ Get channel and single/differential mov $C_treg4 , $C_stTOS \ single/differential bit shl $C_treg4 , # 3 spop \ Add channnel add $C_treg4 , $C_stTOS \ Add start-bit or $C_treg4 , # h10 \ Clear $C_stTOS mov $C_stTOS , # 0 \ Send control data [start_bit + single/differential + channel] to MCP320* shl $C_treg4 , # d27 mov $C_treg5 , # 5 \ set cs to Lo andn outa , $C_treg1 __1 shl $C_treg4 , # 1 wc \ set dpin to Hi/Lo if_c or outa , $C_treg2 \ out clk-pulse jmpret __clk_out_ret , # __clk_out andn outa , $C_treg2 djnz $C_treg5 , # __1 \ set dpin to input andn dira , $C_treg2 \ dummy clock jmpret __clk_out_ret , # __clk_out \ Receive data [Null bit + 12bits] mov $C_treg5 , # d13 __2 shl $C_stTOS , # 1 \ clock out jmpret __clk_out_ret , # __clk_out nop test $C_treg2 , ina wz if_nz add $C_stTOS , # 1 djnz $C_treg5 , # __2 shr $C_stTOS , # 1 \ set cs to Hi or outa , $C_treg1 \ set dpin to output or dira , $C_treg2 jexit __clk_out or outa , $C_treg3 mov $C_treg6 , cnt add $C_treg6 , # d16 waitcnt $C_treg6 , # 0 andn outa , $C_treg3 __clk_out_ret ret ;asm a_mcp320* }