I tried a fast SPI write last night and the timing of the smartpin load and writing data is a little tricky but I may instead combine a 32-bit asynch serial write with the 32 clocks where I write the data first, then wait and write 32 clocks. That way the start bit of the asynch is not clocked but the other bits are. I just need to do a REV to flip the data and a movbyts before sending msb first.
If you guys look in the flash_loader.spin2 program, you can see how a smart pin and the streamer can work together to read the SPI flash at 100% efficiency.
Also, the 2nd example in the DEBUG logic analyzer display captures pin data at full speed. It just takes 2 or 3 instructions to operate.
Yeah streamer use is not hard once you sync to it in the code.
Earlier, I mentioned you'd be able to do 50Mbps SPI based SD transfer with a 50MHz P2, but I forgot you also need to generate a 50MHz clock, so you really still need a 100MHz P2 for that sort of SPI speed.
With HyperRAM the transfer was fortunately DDR so we are able to get the full bandwidth sysclk/1 transfers in that case. For SDR clocked transfers (like SD uses), the P2 still needs to run at 2x the clock rate.
Peter with just a 2x unroll inside the outer RX loop (eg. using 2x REP loops), in the fastest case you could get ~5.5% boost with your bit bang approach if you set x=2 and with clkdly set to 0. Only impact is it consumes 6 more instructions and another register and quantizes from 32 to 64 bit transfers (but for 512 byte SD sectors this is not an issue). Unrolling further helps but gives diminishing returns.
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I tried a fast SPI write last night and the timing of the smartpin load and writing data is a little tricky but I may instead combine a 32-bit asynch serial write with the 32 clocks where I write the data first, then wait and write 32 clocks. That way the start bit of the asynch is not clocked but the other bits are. I just need to do a REV to flip the data and a movbyts before sending msb first.
Should work a treat.
If you guys look in the flash_loader.spin2 program, you can see how a smart pin and the streamer can work together to read the SPI flash at 100% efficiency.
Also, the 2nd example in the DEBUG logic analyzer display captures pin data at full speed. It just takes 2 or 3 instructions to operate.
Yeah streamer use is not hard once you sync to it in the code.
Earlier, I mentioned you'd be able to do 50Mbps SPI based SD transfer with a 50MHz P2, but I forgot you also need to generate a 50MHz clock, so you really still need a 100MHz P2 for that sort of SPI speed.
With HyperRAM the transfer was fortunately DDR so we are able to get the full bandwidth sysclk/1 transfers in that case. For SDR clocked transfers (like SD uses), the P2 still needs to run at 2x the clock rate.
But streamer not available during XBYTE nor hub exec, so fastest possible non-streaming SPI read/write routines are very welcome.
Peter with just a 2x unroll inside the outer RX loop (eg. using 2x REP loops), in the fastest case you could get ~5.5% boost with your bit bang approach if you set x=2 and with clkdly set to 0. Only impact is it consumes 6 more instructions and another register and quantizes from 32 to 64 bit transfers (but for 512 byte SD sectors this is not an issue). Unrolling further helps but gives diminishing returns.