Number of times....

denno · 2021-01-16 14:29

one can WRITE or READ from EEPROM in the Propeller before that part of the EEPROM cell, location wears out?

Thanks...

Peter Jakacki · 2021-01-16 14:38

Unlimited reads but minimum 1,000,000 times typically. Minimum means minimum as I have gone well well over that in various tests.
But remember that internally the EEPROM does the equivalent of a page write and that page can be 64 or 128 bytes, so writing to one byte affects all bytes in the page.

Maciek · 2021-01-16 15:39

IIRC, some EEPROMs from ST are specified at 4.000.000 wrights but it wouldn't hurt to check the relevant datasheet if you have a specific device in mind.

denno · 2021-01-17 14:19

Peter..does writing to one LONG, rewrite the whole page also...32 or 64 LONG(s) also? Probably does...?

Peter Jakacki · 2021-01-17 16:12

If the device has 128 byte pages such as the 64kB (512kb) devices and the longs are page aligned then that is only one page for 32 longs or 2 pages for 64 longs. The 128kB devices such as the M24M01 have a 256 byte page though and I would just use these as they are very cheap these days.
Actually it doesn't count if it does not changed any bits from 1 to 0 apparently. So you could hit the same byte in the page but the wear doesn't affect the other bytes. But too many have worried too much for too long about EEPROM wear. You can write to the same byte every 5 minutes and it would take around 10 years to be around the minimum mark. But wear does not mean failure but it can mean that the cell does not hold the charge as well or for as long, but then again all memory that relies on charges on floating gates such as EPROM, EEPROM, Flash etc will eventually lose some charge and become corrupted. This has been the case with EPROMs programmed decades ago that have suffered from bit rot. So too is the fate of all silicon memory.

denno · 2021-01-17 21:38

Very interesting read, and just a little over my head. I have always wondered, in simple terms, how the memory...aka...cells that store a 1 or a 0 in the EEPROM work. Do you have a web site that explains how this works in...lets say...simple terms. You said "floating gates". Are they a type of MOSFET?

Peter Jakacki · 2021-01-18 00:45

Imagine a capacitor connected to the gate of a MOSFET that is isolated from any other leakage. The gate itself though is a capacitor of sorts and a tunneling voltage is used to break through and charge or discharge that gate. Over time it will leak away and a worn transistor will be more leaky from all the tunneling effects.

Cluso99 · 2021-01-18 01:45

Peter Jakacki wrote: »

If the device has 128 byte pages such as the 64kB (512kb) devices and the longs are page aligned then that is only one page for 32 longs or 2 pages for 64 longs. The 128kB devices such as the M24M01 have a 256 byte page though and I would just use these as they are very cheap these days.
Actually it doesn't count if it does not changed any bits from 1 to 0 apparently. So you could hit the same byte in the page but the wear doesn't affect the other bytes. But too many have worried too much for too long about EEPROM wear. You can write to the same byte every 5 minutes and it would take around 10 years to be around the minimum mark. But wear does not mean failure but it can mean that the cell does not hold the charge as well or for as long, but then again all memory that relies on charges on floating gates such as EPROM, EEPROM, Flash etc will eventually lose some charge and become corrupted. This has been the case with EPROMs programmed decades ago that have suffered from bit rot. So too is the fate of all silicon memory.

OT

Peter, I know you are aware of the following, but it may be of interest to some others on the forum.

Then there is the flow/growth of the silicon metal that effects all usual silicon chips

The metal tracks actually "flow" as the metal is in fact liquid metal and is subject to flow and also grow spurs with age. These effects are more pronounced in chips around 22nm and below because the tracks and spaces are so fine that over time the tracks flow which can create shorts and opens. I read that Intel processor chips (and of course others too) are only guaranteed to last ~10 years before some of these effects could render the chips unreliable. I'm unsure of how much is fact and how much is hype, but there is obviously some truth buried in there.

EEPROM technology (the windowed variety) of memory was fascinating. To program a "bit" you blasted the "fuse(s)" with a high voltage/current (~12V and ~~50mA) the fuse would burn out and the bit would be "programmed". Then if you exposed the chip to UV light for ~30 minutes, those blown fuses would self-heal (grow back) and all would be good for further programming. That is why you should find labels (to block the UV) on the windows of these chips. If you didn't have a label then you could expect problems some time down the track, depending on the amount of UV hitting the chip.

Peter Jakacki · 2021-01-18 02:17

@Cluso99 - There is no fuse to blow or heal, just simply using the "high voltage" tunneling mechanism to change the charge on the floating gate. On UVEPROMs that had a quartz window above the chip, the shortwave UV energy could penetrate deep enough to cause the charge to leak away much faster than normally, thus "erasing" it.

Metal flow has been well understood for a long time and even back in the 70's with actual "fuse" cell technology there was always a problem with whiskers growing (rather than flowing). If no more chips were made for the next 10 years then maybe the only chips that might still be operating are the older chips, and then maybe not unless it used mask ROM. So maybe the P2 and TAQOZ will still be running

Cluso99 · 2021-01-18 07:53

I had a seniors moment and couldn’t remember whiskers so used spurs instead.
We only have to worry about 22nm and below so P2 will be good almost for life.

I always thought the EPROMs were basically fuses which grew back under UV. But i see i have been wrong for the last 45 years

Oh well, I’m still learning at my age

denno · 2021-01-18 18:14

Thanks to all that contributed to this knowledge base. Much appreciated...

Lets say, you program a PROPELLER's EEPROM. So, the gate of the individual cell, through the programming, is charged with a "1" or it is discharged for a "0". That condition, 1 or 0 can be stored for how long?

Right now, I have several Basic Stamps running various watch dog programs on my boat. These programs have been running now for 13 years, non stop. A DO/LOOP, always checking various sensors. Will the program ever fail, meaning a "1" might change to a"0" in a cell?

Would this explain why, some old Radio Shack stuff, would fail after a long period of time? LOL

Peter Jakacki · 2021-01-18 23:20

A charge will leak away but an uncharged gate won't slowly charge. A charge on a gate is read as a 0 which is why a blank memory is read as FF's. Under extreme heat the charge will leak away faster, but it might be decades before it starts to affect the actual data read.

Of course if software would periodically or after reset read the EEPROM and write that data back then this should refresh it although to be sure you would erase then reprogram. However this is risky while it is running in-situ because the power might fail at that moment and then your memory would be corrupted etc.

Tracy Allen · 2021-01-19 20:38

Another option if you really, really want to be sure is FRAM "ferroelectric ram", which can be a drop in replacement for i2c eeprom on either the BASIC Stamp or the Propeller. Like eeprom, it retains its data without power. It is durable, claiming 150 years retention and 10^14 read/write cycles. And it is fast, no waiting for writes. They come in densities from 0.5k x 8 to 128k x 8. Example from Mouser, 32k x 8, FM24V02A is relatively expensive at $6+.

denno · 2021-01-21 21:05

In my last project, which involved the propeller (PROPMINI), and using 6 different COG(s) out of the 8. Each COG is doing a different thing, and then WRLONG or RDLONG (propbasic) to/from the EEPROM. Then one COG that controls the LCD display RDLONG(s) all important data for display.

Question, is it necessary to add a PAUSE 50 "after" each WRLONG and/or RDLONG to give the EEPROM time for it's WRITE.

Tracy, nice to hear from you again. You have helped me in the past with some ultrasonic issues, trying to scare the deer out of my garden...turns out that a fence works better...LOL

The 32k x 8, mentioned above...what software would you use to program that. The "x8" means it has 8 COGs?

Thanks again to all...

Peter Jakacki · 2021-01-22 02:18

Tracy is talking about a replacement for the EEPROM chip, so 32k x8 simply means 32k bytes (x8 bit wide internally). For many memory chips a EEPROM takes 5ms (10ms max) to program a location or page and it only needs a "pause" if you are trying to write within that time and the I2C software doesn't check the device busy flag (just a lack of ack when being addressed). If you are not writing to it immediately after a write, then don't bother pausing. WRLONG/RDLONG is a PASM instruction though although the software can allow you to write a long which is broken up into 4 sequential bytes.

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