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Is there an ANDN equivalent in Spin2?

Alexander (Sandy) HapgoodAlexander (Sandy) Hapgood Posts: 351
in Propeller 2
In PASM, the ANDN instruction is quite handy for clearing individual bit(s) in a register. I can't find a similar function in Spin2. I'm thinking about how you would change the output of an individual pin from 1 to 0.

Sandy

Comments

  • AribaAriba Posts: 2,409
    ANDN exists also in the P2 instructions. Why do you think it's not there?

    But for individual pins there are much better instructions now:
    OUTH, OUTL sets the output High or Low
    DIRH, DIRL sets the direction of the pin
    DRVL, DRVH sets the direction and output with one instruction.
    The parameter is direct the pin number, this works for all 64 pins, not only for Port A or B.

    Andy
  • JonnyMacJonnyMac Posts: 7,318
    edited 2020-11-19 (5:17 PM)
    There are general instructions that will work on any register (though for IO, what Andy showed you is the most efficient). 
    BITL    D,{#}S         {WCZ}
BITH    D,{#}S         {WCZ}
BITC    D,{#}S         {WCZ}
BITNC   D,{#}S         {WCZ}
BITZ    D,{#}S         {WCZ}
BITNZ   D,{#}S         {WCZ}
BITRND  D,{#}S         {WCZ}
BITNOT  D,{#}S         {WCZ}

    Here's a simple bit-bang RX UART that takes in the bits LSB first -- using bitc (C has the new bit) and putting it where it belongs means no mask is needed, and no byte clean-up is required after. 
                    mov       t1, bittix                            ' wait for middle of start bit
                shr       t1, #1
                addct1    bittimer, t1
                waitct1

                mov       t3, #0                                ' clear workspace

rx_byte         rep       #5, #8                                ' 5 (inst) x 8 bits
                 addct1   bittimer, bittix                      ' update bit timer
                 waitct1                                        ' let bit timer expire
                 testp    rxd                           wc      ' sample rx
                 shr      t3, #1                                ' prep for new bit
                 bitc     t3, #7                                ' add to result
    Note, too, that the RX pin is directly sampled into C using testp -- again, no mask required for IO access.
  • RaymanRayman Posts: 11,687
    edited 2020-11-22 (1:27 PM)
    In Spin2 there are the equivalent of these assembly instructions ...

    Things like Pinhigh()

    But maybe &NOT would work in Spin2?
  • Alexander (Sandy) HapgoodAlexander (Sandy) Hapgood Posts: 351
    edited 2020-11-23 (4:27 AM)
    The little bit I know about programming the propellor has been learned using PASM. Basically I know just enough spin to launch PASM code in a cog on the P1. When I started to look at Spin2 I couldn't find an andn equivalent and wondered if I had missed it somehow.

    As I become familiar with the P2 I'm learning that launching PASM code is not particularly hard so I can return to my usual methods.

    Thanks for your input.

    Sandy
  • RaymanRayman Posts: 11,687
    There’s also the new inline assembly...

    With an org and end block.

    Makes using assembly in Spin2 easy.
  • JonnyMacJonnyMac Posts: 7,318
    edited 2020-11-23 (3:59 PM)
    I'm prefer Spin but use a bit of PASM for speed when required. While the new PASM2 instruction set is much larger (by about 5x), much of it seems easier. As discussed earlier, bit manipulation is a lot easier in the P2 than in the P1.

    Inline PASM2 is my favorite thing about the P2. As Ray points out, it makes using small sections (that don't need to run in a cog) very easy. It also facilitates learning PASM2. I use this method for testing PASM2 instructions and code snippets: 
    pub test_pasm2(dvalue, svalue, flagsin) : result, flagsout

  org
                testb     flagsin, #1                   wc              ' set flags
                testb     flagsin, #0                   wz

                rol       dvalue, svalue                wcz             ' instruction to test

                mov       result, dvalue                                ' return modified value
                bitc      flagsout, #1                                  ' return modified flags
                bitz      flagsout, #0
  end
    zip
    zip
    jm_learn_pasm2 - Archive [Date 2020.11.23 Time 06.30].zip
    12K
  • Alexander (Sandy) HapgoodAlexander (Sandy) Hapgood Posts: 351
    The reason I started using PASM on the P1 was the requirement to calculate or, worse, estimate the amount of stack space required when launching spin code into a new cog. Calculating... isn't that what computers are good at?

    Sandy
  • Wuerfel_21Wuerfel_21 Posts: 1,099
    Alexander (Sandy) Hapgood wrote: »
    The reason I started using PASM on the P1 was the requirement to calculate or, worse, estimate the amount of stack space required when launching spin code into a new cog. Calculating... isn't that what computers are good at?

    Sandy

    Thing is, you will rarely if ever need more than 128 longs. Less than 64 for most things you're going to launch into another cog. Starting with that and adjusting up and down depending on need is barely an issue.
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