Any possibility of P2 in QFN package?
frank freedman
Posts: 1,975
Curious if there will ever by a possibility of the P2 in a QFN package. It would be more of an assembly PITA for one-offs, but for production runs, smaller package size, lead spacing etc. may be worth using this form if ever available. The reason for this question comes from the QFP P1 in the middle of the C-3 board as compared with the QFN P1 in the middle of the prop mini (yep, there was one in the last mystery box, a real pandora's box if you will. To bad no emic 2 in there, that would have been fun with the string shooter.) I doubt the mini could have been done with the QFP part without significant trickery for the traces and SMT for the connector pins. The P1 QFP part is a couple mm short of the width of the mini board. Perhaps folding the pins under on the QFP for an old school sort of QFN footprint may save some space, but that would still be a larger footprint than the QFN itself. Also noticed some electrical advantages of the shorter lead lengths etc. while doing a quick comparison lookup of these package types.
Comments
QFN100 is not common, I can find FTDI FT9xx parts with a 8.00mm PAD size, (12x12 body) which may be a bit small for P2 die ?
BGA may be a more practical alternative package ?
If the I/o pins could be at the edges, could be easy to route...
https://c44f5d406df450f4a66b-1b94a87d576253d9446df0a9ca62e142.ssl.cf2.rackcdn.com/2018/02/MicroLeadFrame_DS572.pdf
We'd need to show some volume, I think, before ON would get on board with this change.
Better than qfn for me as can verify connections ..
The trouble with QFN's, especially, is that they oxidize if not kept sealed and then become impossible to solder. Packages with legs are a lot more forgiving.
It is what it is. We should not open up another box. To have a return of investment it will need millions of chips sold. I just now can not imagine which application will give a breakthrough. But it, then money will be found for a redesign, in another technology and as such an unthinkable application most likely will not use every chance the propeller offers, this redesign will most likely be not as symmetrical as we see the P2. So, Chip, if you have some time over, invest it in relaxation and wellness and let the vessel continue in the direction you started it.
In any volume production scenario, most QFN and BGA packages are vanilla so the concerns that some have on the forums are addressed with standard processes. 0.4mm pitch QFNs and 1,166 ball BGAs are a daily occurrence on my production floor, yet they would probably cause heart attacks for many on this forum. Different environment, different desires and expectations.
So, essentially it all comes down to volume. The QFP is perfect for the current expected volumes of the P2. If volumes head the direction we all hope, then I would expect to see a BGA package offering to support improved design offerings.
When I got back my first batch of P1 boards, I used the same sort of go/no go pin function test that I'd used successfully for years with the BASIC Stamp/SX in 44 pin QFP. Namely, the test fixture has as array of RC networks that allow testing for shorts, opens, drive levels, and functioning as both inputs and outputs. The test was sensitive to leakage between pins, and many boards didn't pass, all over the place, never a problem with the QFP Stamp. It came down to flux residue (water based flux) under the chip. Despite pressure washing and surfactants, the assembly house had not gotten it consistently. That took a couple of iterations to resolve. There were other issues too, DFM issues, having to do with solder release and amount of solder on the center pad. The center pad is on one hand an island that all routing has to circumvent, and on the other hand, the center pad is a lake, and the chip has to float on it just so, or all sorts of funny things can happen. Definitely get professional help!
The RCarray test also illustrates the sensitivity of the close spaced, hidden pads to effects like crosstalk and moisture on the circuit board. A design that depends on small currents, for example, a photodiode monitor, or a high impedance sigma delta converter, has to be especially wary of those effects. It's generally less important for digital processing.
It does bother me that the push for the smallest footprints extends to dedicated analog chips like front ends for photodiode amplifiers and potentiometric gas sensors. They would perform better much more easily if the legs were to stick out where you can see them and supply adequate guard traces.
And I do not believe it was anything to do with any pcb design flaw difference either.
https://forums.parallax.com/discussion/comment/1397178/#Comment_1397178
When I soldered my own QFN prototypes, I used rosin flux leaded solder. That flux was non-conductive to start, so the RC tests were pretty good without flux removal. I left the pads long enough on the edge to do touchups, and had pretty good success. It was when I took it to a CM using water soluble flux and lead-free that the RC test problem showed up. They faced a new part and test procedure. They did resolve the problem(s) in the second iteration.
Nevertheless the RC tests were never as good with the QFN as with the QFP. It is simply far easier to see what is going on with those splayed out legs, not just for cleaning the pcb, but in so many respects including troubleshooting. So I'm all in for QFP unless there would be some overriding consideration of heat transfer, or RFI, or board real estate.
With water based flux you save one or two cents but risk a lot of problems anf have a lot or extra work for cleaning.
But I like the idea with QFN being a smaller footprint.
I'm curious. Why is it a less advanced option? I find it equally valid for commercial purposes, while easier to re-flow or rework. The QFP is a great package for industrial purposes, although this particular package is not ideal because of the fine pitch.
Kind regards, Samuel Lourenço
just out of curiosity (I know nothing about PCB's) , why is a BGA better for mass-designed/produced stuff? Is it because of slightly smaller dimensions or production reasons or what else?
Do BGA's position them self better when reflowing? In my thinking all the connections on the bottom would make routing of connections a nightmare, but as stated I know nothing about all of this.
Just curious,
Mike
My two cents.
Kind regards, Samuel Lourenço
I have had to prototype with a small QFN chip before. I simply flipped it over, glued to the board, and soldered small wires to the exposed pads I needed.
It worked, but it was very difficult to solder the wires to the chip because the solder wouldn't 'wick' onto the pads of the chip. Now I assume maybe oxidation was the reason why. I was previously assuming it was because the package was acting like a heat sink
Is there anything I can do about this? A special type of solder? Sand the connections? Maybe my initial assumption is still ALSO correct?
I'm no expert for high volume production but I also like BGA very well. For example a 100 pin 0.8mm pitch BGA package is only 9x9mm. A 100 pin QFN needs a much smaller pitch which is asking for more trouble and it's still much bigger, 14x14mm for 0.5 pitch. 0.4mm pitch is a nightmare.
We did several 1000s of BGA chips with 96 to 484 balls and never had a single soldering problem.
About routing: If the BGA pin layout is clever, I mean power pins in the center and IO pins at the perimeter, then it's no problem at all. Especially not with the propeller because any pin can be used for any purpose. If you don't need all of them you can use the outer pins first and save some layers for the PCB. For a 100 ball BGA you can reach all pins with a four layer board with JLCs standard process (0.2mm min drill, 0.45mm min via, 5 mil traces).
But if the pin layout is random and the chip design has many constraints like with ARM CPUs where a pin can be used only for a very limited set of peripheral functions, then I agree, it's a nightmare to route.
I found out that the simplest way to remove this oxidation was to rub the chip (pads down) on a flat xero paper surface and use good quality gel flux shortly after when soldering the chip. Never encountered any problems with soldering these.
Beware, however, this is only good for a single/very low volume boards. An absolute no go otherwise.
Another difference is with IC fab houses; in some ways BGA packages are more common and thus can present lower costs for volume production of the raw parts if a factory is better geared for them. I think that the current fab that Parallax is using has no issues with the QFP100 package being used, so that may not directly apply to the P2.
In cases where BGA packages are above QFP costs, there are gains in manufacturing to offset them. Handling damage is a key factor with QFPs, where as a dropped BGA can almost always still be used after inspection.
From a functionality perspective, a BGA can provide a shorted path from PCBA pad to die which may present valuable advantages in performance, signal integrity, power management, and thermal management.
For the routing concerns, manufacturers utilizing BGAs for their ICs will typically provide routing guidelines that support the best case scenarios for their part and the package used. When done properly, BGA routing is basic geometry as opposed to an advanced form of art. This all depends on the manufacturer's level of support for the package-based usage of their chip. For example, Octavo Systems has a very well done layout guide for their OSD32MP15x that gives a wealth of information for designing around their BGA-302 package. Also on the page is a nice and clean BGA Ball Map, which does a decent job at showing the thought behind isolation functionality by location to make PCBA design a little easier.
Some of my perspective is based upon that fact that I believe all P2 based designs will be 4-8 layers to create an efficient use of real estate and make trace routing a task that can be accomplished without a lot of heartache. Obviously, the fewer the layers, the harder it will be to keep clean routing goals.
All that said, I still have the same opinion. For now, QFP is the right choice for the P2's early life, but other package offerings should be on the table for P2's future.
Once you have one BGA, and the layers needed to route that, it makes much less sense to mix in lower density packages.
Parallax should certainly ask OnSemi about tooling, MOQ, and package prices for BGA P2, so they are somewhat ready when a higher volume customer rings up
The minimum will be 2 layers, as there are already 2 layer designs being posted.
I think 4(+) layers is more of a sweet-spot for the smaller boards, as the price impact on compact boards is less, and the gains in thermal and electrical performance are significant.