MRAM on the Rise

Here is one for evanh... ;)

https://www.eetasia.com/news/article/18033003-mram-on-the-rise?utm_source=EETI Article Alert&utm_medium=Email&utm_campaign=2018-03-30

“Five years ago, we thought we’d have to fight at 40 nm against flash, which is not the case today,” he said. “Today, the story’s different. The three main foundries have adopted MRAM as a non-volatile memory solution for nodes starting at 28 mm and below, and that there would be no flash available for these nodes. That was good news for us.”

Looks like a 28nm P3 (P4?) would use MRAM, instead of Flash..

There is still Flash activity at 28nm, so there is some overlap to the claim..

http://www.embedded-computing.com/automotive/renesas-28-nm-automotive-control-mcu-integrates-16-mb-on-chip-flash-up-to-six-cpu-cores
"16 MB of built-in flash memory, six 400 MHz CPU cores and deliver up to 9600 MIPS"

Comments

  • Damn straight!

    /me does a dance. :)

  • evanhevanh Posts: 9,854
    edited 2018-09-01 - 03:32:31
    Think I might have found a real competitor to MRAM. Called NRAM - https://www.eetimes.com/document.asp?doc_id=1333622

    I'm unsure of its endurance though. In fact it's so new I suspect no-one is sure of its endurance, but everything else about it looks really amazing. I found a PDF comparing NRAM to PRAM and ReRAM and how it has better endurance than either of those but sadly MRAM was not on the comparison list. Presumably because MRAM beats it on that point - https://www.flashmemorysummit.com/English/Collaterals/Proceedings/2016/20160811_S301A_Ning.pdf

    It feels odd visualising this as a mechanical switch that can happily toggle at MHz!

    EDIT: NRAM might end up being a Flash rather than DRAM replacement. That would still leave MRAM as the ideal DRAM replacement. It all depends on the endurance. Time will tell.
  • jmgjmg Posts: 14,480
    evanh wrote: »
    Think I might have found a real competitor to MRAM. Called NRAM - https://www.eetimes.com/document.asp?doc_id=1333622

    I saw that go past - as you say, short on hard data and at the experimental / funding rounds level.
    They will be worth watching, but the memory marketplace is very conservative around new technology.

  • Hmm, "conservative" has that emotive attribute. It is the correct term though. There is a chicken or egg feedback because of the size of the mass market and the race to fully utilise cutting edge production. Hence the reason for saying NRAM could be drop-in replacement DDR4 DIMM.

  • Conservative, as in low cost, low risk, has gotten a bit of an underdog status in the popular lexicon, due to it's other use.

  • Ummmm, MRAM storage is based on electron spin. It is VERY long term. It stays until something changes it. Electrons, ALL of them, are always spinning and unless acted upon, they don't change.

    evanh wrote: »
    Think I might have found a real competitor to MRAM. Called NRAM - https://www.eetimes.com/document.asp?doc_id=1333622

    I'm unsure of its endurance though. In fact it's so new I suspect no-one is sure of its endurance, but everything else about it looks really amazing. I found a PDF comparing NRAM to PRAM and ReRAM and how it has better endurance than either of those but sadly MRAM was not on the comparison list. Presumably because MRAM beats it on that point - https://www.flashmemorysummit.com/English/Collaterals/Proceedings/2016/20160811_S301A_Ning.pdf

    It feels odd visualising this as a mechanical switch that can happily toggle at MHz!

    EDIT: NRAM might end up being a Flash rather than DRAM replacement. That would still leave MRAM as the ideal DRAM replacement. It all depends on the endurance. Time will tell.

  • veluxllc,
    Endurance is about cell damage (life expectancy), not data retention time or error rate. I have noticed on Wikipedia, that the two get mixed up or even combined at times.

  • evanhevanh Posts: 9,854
    edited 2018-09-27 - 08:02:22
    Here's an example of something written about endurance from the MRAM article - https://en.wikipedia.org/wiki/Magnetoresistive_random-access_memory#Endurance
    wikipedia wrote:
    If the read current/write current ratio is not small enough, read disturb becomes more likely, i.e., a read error occurs during one of the many switching cycles.
    That's clearly error probability which can be classed as a form of data retention. Certainly not damage to the memory cell hardware.

    EDIT: Not a well written piece at all. Looking at the edit history of that article, I can see the same author added all for sections Retention, Endurance and the Overall table.

    One only expects that confusion when multiple authors are each adding little edits over time. He managed to make a mess all on his own.
  • jmgjmg Posts: 14,480
    another update for evanh ...

    https://www.edacafe.com/nbc/articles/1/1780319/Apollo4-SoC-Family-Ambiq-Redefines-Ultra-low-Power-Battery-Powered-Intelligent-Endpoint-IoT-Devices-featuring-Always-on-Voice-Processing

    The Apollo4 SoC family is implemented on TSMC® 22nm ULL process and based on a 32-bit Arm® Cortex®-M4 processor with FPU and Arm Artisan® physical IP
    Achieving an unmatched 3 μA/MHz from MRAM with low deep sleep current modes
    Up to 192 MHz clock frequency using TurboSPOT™
    With up to 2MB of MRAM and 1.8MB of SRAM, the Apollo4 has enough compute and storage to handle complex algorithms and neural networks while displaying vibrant, crystal-clear, and smooth graphics.
  • evanhevanh Posts: 9,854
    edited 2020-09-15 - 06:28:07
    It should be all MRAM, it'd be able to easily fit 8 MB of MRAM if the SRAM was ditched.

    There's something weird about that Apollo4 design. Looking at the datasheet - https://secureservercdn.net/72.167.242.48/9xy.011.myftpupload.com/wp-content/uploads/2020/09/Apollo4_MCU_Data_Sheet_v0_7_0.pdf it only lists reads of the MRAM. Seems to be treating it like Flash memory. Defeats the real usefulness of MRAM and it may as well be Flash instead.
    Apollo4 MCU incorporates a NVM cache to the ICode and DCode path from the microcontroller. This
    controller is intended to provide single cycle read access to NVM and reduce overall accesses to the NVM
    to reduce power. The controller is a unified ICode and DCode cache controller. The cache fill path is
    arbitrated between cache misses as well as the other NVM read agents (Info, Reg, BIST).Caching is
    supported for the entire 2 MB internal NVM and all MSPI apertures. The cache is configurable 2-way set
    associative or direct mapped, 128b line size.
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