Conflicting official PLL limits?
JRoark
Posts: 1,215
I'm looking at the "Parallax Propeller 2 Documentation - 2020-06-05 - v33 (Rev B/C silicon)" document and I see conflicting information about the range of allowable PLL frequencies. Perhaps brighter minds than mine can chime-in here with some guidance.
In the table on page 52, under the definition of the "%MMMMMMMM" bits, it says the range is 100 to 350 mhz:
"This divided VCO frequency feeds into the phase-frequency comparator's 'feedback' input. This frequency division has the effect of multiplying the divided XI frequency (per %DDDDDD) inside the VCO. The VCO frequency should be kept within 100MHz to 350MHz".
But then on Page 53, in the example, it says this:
"PLL Example: The PLL's VCO is designed to run between 100MHz and 200MHz and should be kept within that range".
Which is correct?
In the table on page 52, under the definition of the "%MMMMMMMM" bits, it says the range is 100 to 350 mhz:
"This divided VCO frequency feeds into the phase-frequency comparator's 'feedback' input. This frequency division has the effect of multiplying the divided XI frequency (per %DDDDDD) inside the VCO. The VCO frequency should be kept within 100MHz to 350MHz".
But then on Page 53, in the example, it says this:
"PLL Example: The PLL's VCO is designed to run between 100MHz and 200MHz and should be kept within that range".
Which is correct?
Comments
The design limits are 200MHz, but many are running the P2 above that, in what is really over-clocked mode, but a higher MHz spec (still not 350MHz!) could be more formally supported if Parallax offer higher MHz, at tighter Voltage and Temperature specs. More batches of P2's may be needed for them to offer that. Other vendors do this - spec different MHz vs Vcc & temperature.