could you please explain theese workarounds a bit more? The coupling is capacitive, so if I understand correctly there is no DC error. And if I have enough spare pins I could ground every second pin between the ADC inputs and the error could be neglected?
Yep. You may as well tie each pair together so they both see the same instead of grounding every other, but both options are suitable.
... Chip discovered a performance issue with the A/D where neighboring inputs were causing some capacitive coupling, reducing the resolution of the A/D to something low - like four bits instead of 14 bits. The ways around this were to couple A/D pins together, skip A/D inputs to every other pin (and ground the ones in between), or just accept slow frequency sampling.
Hello Ken,
could you please explain theese workarounds a bit more? The coupling is capacitive, so if I understand correctly there is no DC error. And if I have enough spare pins I could ground every second pin between the ADC inputs and the error could be neglected?
For example, if I drive a motor with a PWM power stage and measure the winding current with hall current sensors and if I sample the analogue voltage over a complete PWM cycle then all capacitively coupled errors should be cancelled out, right?
I'm currently designing a new product and I have to decide if I give the P2 another chance or not. Waiting until Oct 2020 is a no-go. I can live with some restrictions as long as there are workarounds. But I'd need engineering samples ASAP and at least small production volume (~100 units) the next 1/2 year.
ManAtWork, you can do those things you mentioned to make the current silicon work for your app. The coming silicon won't need those accommodations, though. For fast measurements, capacitive coupling will cause apparent DC errors in the conversions. Tying pins together, or even using a pin whose odd/even neighbor is being driven to a steady state, is sufficient to stop unwanted noise.
If you need 100 chips, we can likely work that out. Ken is aware of your post, but he's travelling right now. He will pm you when he has a chance.
Yesterday, I've posted on my blog that the P2 was due to be released in April or May. That seems not to be the case, after all. I wonder if Parallax can recoup the costs.
Does this have to do with the capacitive coupling we have saw in the scope demo, by the way? It seems to be very similar in nature. However, how can I be sure that the board layout doesn't have a part on this?
Also, is Parallax considering fixing the IO ring susceptibility to latch-up at 40% above the nominal voltage?
Yesterday, I've posted on my blog that the P2 was due to be released in April or May. That seems not to be the case, after all. I wonder if Parallax can recoup the costs.
Does this have to do with the capacitive coupling we have saw in the scope demo, by the way? It seems to be very similar in nature. However, how can I be sure that the board layout doesn't have a part on this?
Also, is Parallax considering fixing the IO ring susceptibility to latch-up at 40% above the nominal voltage?
Kind regards, Samuel Lourenço
Samuel, we are just cutting the PinB trace on the ADC input circuit to eliminate the signal coupling within a 500kohm resistor array. There's nothing that can be done on the outside of the chip to stop the coupling, other than doubling up the pins for ADC use or making sure the neighbor pin is not switching.
Adding guard rings would require many new masks and would probably cost $60k. We are going to rate this chip at 4.0V absolute max on VIO, instead of 4.62V. When we build another family member, we'll address the N-wells.
We will get as many risk production parts as possible from this next wafer batch in April. We should get 1,000 chips, which we'll use to support development. If someone has a product need, we will support them as well as we can until we get bigger volumes of chips.
Comments
ManAtWork, you can do those things you mentioned to make the current silicon work for your app. The coming silicon won't need those accommodations, though. For fast measurements, capacitive coupling will cause apparent DC errors in the conversions. Tying pins together, or even using a pin whose odd/even neighbor is being driven to a steady state, is sufficient to stop unwanted noise.
If you need 100 chips, we can likely work that out. Ken is aware of your post, but he's travelling right now. He will pm you when he has a chance.
Does this have to do with the capacitive coupling we have saw in the scope demo, by the way? It seems to be very similar in nature. However, how can I be sure that the board layout doesn't have a part on this?
Also, is Parallax considering fixing the IO ring susceptibility to latch-up at 40% above the nominal voltage?
Kind regards, Samuel Lourenço
Samuel, we are just cutting the PinB trace on the ADC input circuit to eliminate the signal coupling within a 500kohm resistor array. There's nothing that can be done on the outside of the chip to stop the coupling, other than doubling up the pins for ADC use or making sure the neighbor pin is not switching.
Adding guard rings would require many new masks and would probably cost $60k. We are going to rate this chip at 4.0V absolute max on VIO, instead of 4.62V. When we build another family member, we'll address the N-wells.
We will get as many risk production parts as possible from this next wafer batch in April. We should get 1,000 chips, which we'll use to support development. If someone has a product need, we will support them as well as we can until we get bigger volumes of chips.