SA tracking generator as field-expedient P2 clock source?
JRoark
Posts: 1,215
I want to go hunt the upper limits of the P2’s non-PLL speed capability, but I lack a suitable clock source. Tonight it hit me that I might be able to use the tracking generator from my spectrum analyzer for this task. The output does -20db to 0db, which from my understanding, if capacitively coupled to XIN, should be in the normal crystal range.
Am I milking without a bucket here, or would this be workable? I’d really want to see how far the P2 can be pushed with the PLL out of the way.
Am I milking without a bucket here, or would this be workable? I’d really want to see how far the P2 can be pushed with the PLL out of the way.
Comments
The logic stability threshold is on a slightly different thermal slope to the PLL natural limit. At higher temps, say >20 oC, the PLL runs slow enough to prevent crashes from logic timing limits. But at lower die temperatures the PLL gets fast enough to cause crashes if you don't cap the set frequency. The exact limit of that cap is higher as the die temperature is lowered.
This then leads to the need for the thermal pad to be placed directly on a real heatsink rather than a bunch of vias in the PCB.
You won't get far at all without that.
FWIW, many RF mixers need more than 0dBm input power for their local oscillator. 10dBm is 2Vpp into 50 ohms. It's easy to find a wideband amplifier with 10dBm output.
It's going to be tough to wiggle a pin at CMOS levels to 300MHz+, as well as get it past the P2 pin amplifiers.
Most clock generators only spec 250MHz on their CMOS modes, but maybe you can 'overclock' them.
I ordered a cheap 10 db stripline-type broadband amp. This will hopefully arrive tomorrow and I’ll have some data to share over the weekend.
Chip’s comments intrigue me. A P2 at 400+ mhz would be amazing if it was proven stable. And since Peter is prepping the P2D2 for exactly this possibility, it makes warp speed very accessible to us mere mortals without much hacking.
This is gonna be fun.
A 3-inverter ring oscillator in our 180nm process runs at 5GHz.
A 3-inverter ring oscillator in the 14nm process run at 200GHz. That's 40x faster.
Who knows what would be possible?
I think they both ran around 80MHz, but we used much newer FPGA's to develop the P2, which is a much more complex design than P1.
A Prop with a Ghz speed rating does set the mind aglow with possibilities.
Toto... We’re not in Kansas anymore!
4k HDMI wouldn't require any special hardware, just (fast) pins.
In 14nm technology you can get 2MB (2M bytes, not bits) of hub RAM in 1 square mm. 16MB would be no problem.
At 8.6 GHz, a 32-bit counter would roll over TWICE every second.
Bean
I'm really pleased that Parallax is already looking forward to the next thing. Once the P2 hits the formal release phase, and the crush for docs/tools lets up a bit, it seems natural that Chip would look at doing a process shrink while bumping-up the internals. Will it be a P2-XP (eXtreme Performance), or a P3? Or something completely different? Maybe Chip can tease us a bit more with his thoughts.
(I do wonder if @"Ken Gracey" is reading this thread and giving serious consideration to dumping Egg Nog on his corn flakes and calling-in sick for a week. hehehe).
I think the XI feeds the internal amplifier and XO is just xtal drive, but you should be able to get a rough gain plot XI to XO too, which is useful for Xtal usage.
It would also be interesting to know what signal levels (AC Coupled) P2 needs for reliable clocking, by MHz.
That may be a bathtub curve: very low MHz will need some slew-rate boost, and very high MHz need to compensate for simple loss of gain.
The PLL switch over tests, suggest P2 can hang if it gets very narrow clock signals.
That's an interesting idea. We could clock the P2 with the tracking generator output and then hook the XOut to the SA's input and compare gain and noise. This would be roughly similar to doing an "upside-down" SWR plot, but measuring gain instead of loss. We'd just run the sweep across a very wide range (1 mhz to maybe 500 mhz?) and sweep the TG very, very slowly. We could simultaneously validate P2 operation by setting-up some code to toss some bits at a pin at perhaps 1/1000th the clock rate and monitor this output with a scope.
Does anyone know if selecting mode %01_10 via HUBSET enables the output amp on XOut? Any ideas what the roll-off on this amplifier/feedback circuit coming out off XOut looks like?
The Xtal amp is enabled by the CC bits, and is on for not 00.
I did a simple RF probe gain test with 26MHz and 38.4MHz clipped sine sources.
Both worked, and 26MHz was gain > 1 and 38.4MHz showed gain somewhat less than 1 (added Caps = 0pF)
Clipped Sine Osc have a source impedance of ~ 180 ohms
In the meantime I’m trying to fabricate something that will handle 350-500 mhz and give me some gain because the TG output is just short of what the P2 needs to reliably operate. Judging from the results I got using a capacitively coupled freq generator as the clock input, the P2 seems happiest with a swing bigger than about 1.5 volts p/p at 20 mhz while the TG output is about 1.25 v.
I’ll keep banging on it until the beer runs out or I break it. The smart money would probably bet on the latter.
Yup. 1 meg to either rail was my last attempt but this value needs some refining.
Edit: @evanh It sounds like you have some working knowledge of this beastie. Any hints on what might make a good starting point for the divider and coupling cap values? I’m basically doing a cut-and-try based on my gut. Any input appreciated!
What triggered my thinking on this one was the closeness of the voltage needed to VIO/2.
I stated things backwards. I just fixed my prior post. XI is driven negatively with a 1 megohm resistor.