In my video driver stuff I would quite like to add a parallel RGB output mode but have an issue with generating CLK and DE from the same video COG on arbitrary pins.
The CLK should be easy enough to generate as long as it's an integer divider ratio from the P2 system clock (perhaps with non-50% duty cycle if the pixel divider is odd). But the DE output pin may have pin restrictions on where it can be placed. I'm not sure we can send it to any old pin. It may need to come from the streamer hsync output on one of the the lower 8 pins below RGB to keep it synchronized with the data.
I think I asked this a long time ago and @cgracey
mentioned if you use the streamer, it would take over the pin outputs and you can't have a smartpin use the same pin group, but if he did a respin he might be able to fix this limitation (I'd have to dig up the old thread where it was first raised). So if it wasn't fixed in rev B it might still be the case that you'd need DE on the 8 pins below to be able to direct the hsync control to it from the streamer, and CLK on one of the 8 pins outside the 32 pin streamer group so the streamer doesn't override it. This will have some impacts on board layouts etc and may push CLK/DE to different portA/portB groups.
Is there some better way to be able to allocate the CLK/DE pins more freely for parallel RGB LCD use? How could you setup a smartpin to reliably remain in sync with the streamer if you want a DE signal output, where DE is high for active video low for otherwise inactive(blanking) periods?