Frequency range on XI pin ?
Bean
Posts: 8,129
in Propeller 2
Reading the datasheet it says 10MHz to 20MHz on the XI input.
Is this range only for crystals ? Or is it limited to that for a frequency input too ?
In other words, can I feed in a 50MHz signal to XI ?
Bean
Is this range only for crystals ? Or is it limited to that for a frequency input too ?
In other words, can I feed in a 50MHz signal to XI ?
Bean
Comments
Interestingly the 5P35021 clock generator outputs frequencies up 500MHz in a QFN20 and the price is still around a modest $4. Maybe I can accommodate that part on the reverse side of my latest P2D2 as a special option.
Do they make a board to demonstrate that chip? I just wonder what frequency the P2 could run at.
I can do that with my communications service monitor. (Up to 1GHz)
How much drive is needed? What should I do for clock timings? This might be fun!
It just has to go above and below the logic threshold, which is about 1.65V. If you could make a 3.3V peak-to-peak signal, you could capacitively couple it to the XI pin. Right now, we know that the PLL maxes out at around 390MHz, while the main logic still works. There could be a few 10's of MHz more speed possible, but we don't know.
In practice there will be 3 numbers of limits.
Crystals - These will have the lowest upper MHz and it will depend on lowest CL and lowest ESR too.
It is common for MCUs to spec 25~33MHz as Xtal limits, but I'm not sure this has been tested/defined yet on P2.
Some new MCUs do spec 48MHz Xtals, tho the P2's CL choices are not well matched to such high MHz use,
Clipped Sine sources : These AC couple into XI, and I've tested 26MHz and 38.4MHz, and the 38.4MHz case shows measurable less gain across XI-XO (actually a slight loss),
so the upper limit on these is tbd, but may not go as high as 48~52MHz
Direct CMOS drive : This will allow the highest MHz, but still has to get past the pin buffer and ESD filters etc.
It is rare to see CMOS drive specified above 200~250MHz, most clock generators flip to differential modes, which P2 does not support, so that's likely a practical limit.
The Si5351A on P2D2 can go to something just above 200MHz, so it can give a quick test of CMOS in, and probably an indicator for AC coupled in too.
Finding a part that does CMOS to high MHz is not going to be easy.
Digikey has many Oscillators at 250MHz, but nothing stocked above 250MHz
eg my Si544 data says "0.2-325 MHz (CMOS available to 250 MHz)"
The evaluation board is EVK5P35021
Yep, I can accommodate that. How should I set the clock configuration?
It looks like the buffer-take off point is from XI, which means the XI-XO gain/loss does not matter
Addit: If you are setting up a signal generator, can you also do a sweep at 0.8V~0.9V p-p, AC coupled, as that's the common clipped sine amplitude.
Zo on those seems to usually be 180~200 ohms.
Be nice to know where that stops clocking P2.