New P2 Silicon

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Comments

  • Wow! That's a big boy there Mike. I thought I was getting excessive with a 7 port switched hub.
  • Thanks Mike in that case I am covered!!
  • I would be interested in a signed board also.
  • Is that 16 port hub going to have ground loop issues? I have ruined a lot of Propeller chips with ground loops caused by a powered hub introducing 48 volts on the ground side of a USB cable.
    Jim
  • My Eval board + HyperRAM arrived today. I will be doing an unboxing video. Does anyone know if there is demo code for the HyperRAM to validate proper operation?
  • ke4pjw wrote: »
    My Eval board + HyperRAM arrived today. I will be doing an unboxing video. Does anyone know if there is demo code for the HyperRAM to validate proper operation?

    Don't know if this went anywhere:
    https://forums.parallax.com/discussion/169915/hyperram-timing
  • PublisonPublison Posts: 11,716
    edited 2019-11-12 - 19:17:06
    There is a .bas file buried in this thread.

    http://forums.parallax.com/discussion/170553/notes-and-progress-for-the-new-64004-es-hyper-memory-accessory

    Callout to Parallax. What do you use to verify the boards?
  • We used a program that ozpropdev wrote. I sent him a message to see if it's okay to post it, but it's in the middle of the night in Oz, so he won't get it until his morning.
  • We used a program that ozpropdev wrote. I sent him a message to see if it's okay to post it, but it's in the middle of the night in Oz, so he won't get it until his morning.

    Thanks David. They are fighting fires also. Hope all is well with them.
  • Publison wrote: »
    We used a program that ozpropdev wrote. I sent him a message to see if it's okay to post it, but it's in the middle of the night in Oz, so he won't get it until his morning.

    Thanks David. They are fighting fires also. Hope all is well with them.

    No worries David, go ahead.
    I'm a long way south of fires here, so all is well. :)
  • cgraceycgracey Posts: 13,076
    edited 2019-11-18 - 19:48:56
    On Semi got the latch-up testing done. No problems!

    They tested for +/-100 mA at 4.3V:

    Latchup_Test_Results.png
    589 x 204 - 30K
  • Good stuff. Bet that feels good Chip! Big smile.
  • So, was this on a new run? Does that mean that it satisfies all QA related issues with the testing? Full steam ahead with production chips?
  • cgraceycgracey Posts: 13,076
    edited 2019-11-18 - 20:16:46
    ke4pjw wrote: »
    So, was this on a new run? Does that mean that it satisfies all QA related issues with the testing? Full steam ahead with production chips?

    It's the new silicon. It can't handle huge over-voltage on VIO due to voltage-induced latch-up that can occur at >4.3V, but it passes ON's standard current-induced latch-up test at 4.3V.

    For this silicon, we are going to probably call it final, for now. We will give it a max VIO rating of 4.125V, instead of ON's normal 4.62V. Any derivative chip we make in the future will incorporate guard rings around the non-VIO N-wells to increase voltage-induced latch-up immunity to above 4.62V.

    What we have now seems to be working quite well. To add those guard rings to up the VIO max rating would take $60K and 4 more months, at least. What we have is quite decent, it seems - just gets a lower-than anticipated VIO max rating.

    So, this was the final hurdle with ON to moving the chip to production. We can go there now!
  • Another Chipmas coming. Final product! Nice Chip!
  • Seems like we should test out Rev.B a bit first, right?
  • YES!

    Great news Chip.

  • Yes, we don't know of any bugs, yet, but there may be some. We aren't going to press the button for a few more weeks, anyway.
  • jmgjmg Posts: 14,492
    cgracey wrote: »
    So, this was the final hurdle with ON to moving the chip to production. We can go there now!...
    Yes, we don't know of any bugs, yet, but there may be some. We aren't going to press the button for a few more weeks, anyway.

    Sounds good.
    cgracey wrote: »
    ... We will give it a max VIO rating of 4.125V, instead of ON's normal 4.62V..

    That's +25% on nominal 3v3, so that seems fine.

    cgracey wrote: »
    On Semi got the latch-up testing done. No problems!
    They tested for +/-100 mA at 4.3V:
    -100mA is easy to test, but did they clamp VIO at 4.3V, and then inject +100mA for the upper test ? (making IO pins ~5V clamping )
    Or does that mean they limit IO pins to 4.3v OR 100mA which ever comes first. (I guess the former?)

    What current injection is actually needed, in order to trigger latchup, for each +/- direction & does that vary much per pin ?

    Another MCU datasheet I have mentions 400mA test levels.
    Pin current for latch-up -400 ~ +400mA




  • So, assuming no changes to the current 8-cog Rev-B design (like adding guard bands), will there be any differences between the current sample chips and chips from the first production batch (other than labeling)? Will they be equally robust? Will they behave the same way thermally? Will the same packaging company be used? I think these things were mentioned previously, but I forgot the details (and sometimes things change).
  • jmgjmg Posts: 14,492
    So, assuming no changes to the current 8-cog Rev-B design (like adding guard bands), will there be any differences between the current sample chips and chips from the first production batch (other than labeling)? Will they be equally robust? Will they behave the same way thermally? Will the same packaging company be used? I think these things were mentioned previously, but I forgot the details (and sometimes things change).

    They would be `identical`, as they use the same silicon masks, same FAB process, same testing and same package. (only the very few glob-tops were hand crafted)
  • JRetSapDoogJRetSapDoog Posts: 847
    edited 2019-11-18 - 21:43:11
    I see. Thanks. Yeah, I guess the glob-tops were somewhat more vulnerable (with regards to the bonding wires) and maybe less thermally conductive.

    So, with the current samples, it would seem that the answer to the whiny question "Are we there yet?" is "Yes!" But we're still driving around the parking lot looking for a good place to park.
  • That's great new Chip!

    This question is directed to the others: What would be the best way to interface with 5v TTL? ( I am thinking in the 3Mhz range) I don't think a resistor will work, as once latch up occurs, that's all she wrote.
  • RaymanRayman Posts: 11,349
    edited 2019-11-18 - 23:34:22
    I'd think series resistors will work for 5V input, just like it did with P1.
    Actually, I'm already using this on my P2 board as I have FT231X running with 5V I/O and 10k series resistors to rx/tx...
  • Another question directed to others - What would be the best way to interface the smart pin DAC and ADC to the maximum usable MHz frequency of the P2 chip?
  • im curious....how fast is the prop 2 going to be?
  • Fast :smile:
  • Fast enough that Spin 2 bytecode on P2 is likely to execute at speeds comparable to P1 PASM.
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