My first P2 PCB (it's alive!)

RaymanRayman Posts: 9,805
edited 2019-11-15 - 15:25:45 in Propeller 2
I'm working to get this done before chips arrive...

There's a lot of stuff here that's new to me, so this board is somewhat experimental...

Here's some stuff it's got:
HDMI
uSD
HyperRAM
Raspberry Pi Zero interface with EEPROM
RTC
2x Nunchuk
USB
2x Eval Board compatible headers
9-axis accelerometer

Update: The attached Eagle files have fixed the issues so far with this board, TEST now tied to GND, Pullup on RESn, Pullup on CSn of flash chip and replaced micro-USB connector. Warning: Not a proven design.
Prop Info and Apps: http://www.rayslogic.com/
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Comments

  • Nice! What are those two connectors on the left?

    Kind regards, Samuel Lourenço
  • Those are the wii nunchuk connectors...
    Prop Info and Apps: http://www.rayslogic.com/
  • Looking good @Rayman! Nice choice on the Nunchuk port. Could be a cool little game system.
  • samuellsamuell Posts: 449
    edited 2019-11-08 - 11:39:55
    Rayman wrote: »
    Those are the wii nunchuk connectors...
    I see. Those sit through the PCB, right? I think there are through-hole versions of those connectors that solder on top of the PCB, so the risk of pulling one off, and therefore destroying some pads, is greatly reduced. And they would be level with the USB type A connector on the front, thus improving aesthetics, IMHO.

    Kind regards, Samuel Lourenço
  • I'm not too worried about the stuff on the edges of this board...

    I'm mostly hoping that the SMT parts work, so that I can reuse the stencil for future boards...
    Prop Info and Apps: http://www.rayslogic.com/
  • I am very interested to see if I can interface with Raspberry Pi Zero W.

    This gives me a GPU with 2D and 3D graphics and 1080p output.
    Also provides Bluetooth and WiFi.

    I'm hoping I can turn it into a slave device (even though it wants to be master...).
    Prop Info and Apps: http://www.rayslogic.com/
  • jmgjmg Posts: 14,019
    Rayman wrote: »
    I am very interested to see if I can interface with Raspberry Pi Zero W.

    This gives me a GPU with 2D and 3D graphics and 1080p output.
    Also provides Bluetooth and WiFi.

    I'm hoping I can turn it into a slave device (even though it wants to be master...).

    Yes, a nice combination.
    I've seen LCDs for Pi's that talk 125MHz SPI, wonder if a P2 can slave at that speed ? (or how easy that driver is to scale?)
  • evanhevanh Posts: 8,072
    edited 2019-11-08 - 22:27:32
    Given we'll be talking about independent Pi sysclock and prop2 sysclock, a crystal each, and the prop2's synchronous serial smartpin modes are not a true synchronous clocking mechanism, ie: the prop2 really treats the SPI clock as an enable input. That means the timings will follow asynchronous rules.

    Experience suggests the prop2's sysclock will need the be at least 3x the SPI clock to be reliable. 3x 125 = 375 MHz.

    EDIT: That may actually be too optimistic. That's based on the performance of the asynchronous serial smartpin behaviour, which has no separate clock and data. The existence of SPI clock may increase the oversampling needs to 6x the SPI clock.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • roglohrogloh Posts: 1,446
    edited 2019-11-09 - 03:11:34
    jmg wrote: »
    Rayman wrote: »
    I am very interested to see if I can interface with Raspberry Pi Zero W.

    This gives me a GPU with 2D and 3D graphics and 1080p output.
    Also provides Bluetooth and WiFi.

    I'm hoping I can turn it into a slave device (even though it wants to be master...).

    Yes, a nice combination.
    I've seen LCDs for Pi's that talk 125MHz SPI, wonder if a P2 can slave at that speed ? (or how easy that driver is to scale?)

    For higher throughput it could be interesting to try to target using the SMI (secondary memory interface) mode of the RasPi pins. There's not a lot of documentation out there for it but there is a working driver available online. From memory it is a 16/18 bit parallel interface mode that looks a bit like a small register file/32 entry SRAM. ie. CS/RD/WR Address and Data etc. Could potentially give faster transfer speeds of bulk video data etc though SPI is more universal. I think this person already managed 44MB/s over it and more might be possible:

    https://github.com/fenlogic/IDE_trial

    I've always wanted to attempt a project to hook up the P1/P2 to a Pi this way, but haven't got around to try it.
  • Nice find, Roger.

    The Pi I2S interface supports slave clocks. I haven't tested that. In master mode it can run at 250mbps. Although at those speeds it can be challenging to keep the fifos full, even though they are larger than the SPI controller. The pins probably can't handle that data rate anyway. Although, it should be able to do about 100mbps in each direction full duplex.



    Rayman, check the trace widths for Vdd. I'm not sure if they will handle the current needed.
    James https://github.com/SaucySoliton/

    Invention is the Science of Laziness
  • Ah, yes, if the Pi can handle being an SPI slave then that should solve the issue with independent sysclocks.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • The Raspberry Pi Zero W is amazing... Just got into it over Wifi, not keyboard or mouse or monitor needed...
    Now have Samba going and it now looks like a shared drive on my Windows box.

    I think I should have connected the rpi UART to P62, P63 and used a GPIO to connect to reset.
    I'm thinking that would have let me program the P2 over wifi using SSH terminal...
    That would be fun, but not one of my goals at the present...
    Prop Info and Apps: http://www.rayslogic.com/
  • Who is the best outlet to surfacemont the p2 boards? in the U. S. ?
    I have not played with surface mount in a toaster oven. Any leads

    “Light thinks it travels faster than anything but it is wrong. No matter how fast light travels, it finds the darkness has always got there first, and is waiting for it.”
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    Once when you are born
    And once when you look death in the face”
  • Do you mean assemble a P2 board?
    I’ve used screaming circuits before.
    They are fast...
    Prop Info and Apps: http://www.rayslogic.com/
  • RaymanRayman Posts: 9,805
    edited 2019-11-14 - 19:28:47
    Populating the first board now...

    Just realized I didn't add any pull ups or pull downs on the boot Flash/uSD pins...
    What happens in this case?

    Just looked up the table... Looks like always goes to serial...
    801 x 613 - 12K
    583 x 337 - 14K
    Prop Info and Apps: http://www.rayslogic.com/
  • JRetSapDoogJRetSapDoog Posts: 803
    edited 2019-11-14 - 20:50:37
    So, you'd like a pull-up resistor on P61 to get the flash chip into the boot sequence? I'm stating the obvious, but on the flash chip, maybe you could solder a resistor on top of the flash chip straight across from pin 1 (CS) to pin 8 (VCC) opposite, or perhaps solder an SMD resistor from pin 1 (CS) down to the pin 3 (WP) which is already tied high. Neither of those solutions would be too offensive in terms of aesthetics (barely even noticeable). The main thing is just to get it working at this point for a first P2 board. And I'm sure that you will based on your past successes.

    [By the way, I'm assuming that pin 1 of the flash chip is at the top-left in your design image and that the actual/physical pin-out arrangement differs from the "layout" for your schematic symbol of the flash chip. I've never used such an SPI flash chip, but I checked a few pin-outs from different manufactures just now and I think that makes sense for your image and schematic.]
  • I stole that symbol and footprint for the flash chip from Parallax.
    I noticed the symbol has pins in wrong places too. But, it's actually connected the right way.
    That's OK.

    But, I do have a major problem somewhere on the board...
    It won't identify and found that RESn is being pulled down by the P2 chip instead of pulled up...
    Prop Info and Apps: http://www.rayslogic.com/
  • JRetSapDoogJRetSapDoog Posts: 803
    edited 2019-11-14 - 22:20:39
    Hope you get to the bottom of it. As for me here in the peanut gallery, I don't have any idea how to best handle the reset line, not that you're asking me, of course. But anyway, in your PCB image, it looks like it goes to a transistor up "north." And I think it also wanders way over to the right side of the board and then upwards (but it's hard to tell from that image as some traces get "blurred" with the copper pour(s) on the bottom side).

    Anyway, was just searching the forum now for related info, and about three years ago, I believe folks were saying then that the reset line was only an input and that the P2 couldn't drive it. But then that may have changed to accommodate resetting flash chips that are available from certain vendors. Not sure about that, but I see that you were a big part of that discussion, so you undoubtedly know. And you're saying that the P2 is holding the line low (as opposed to something else), so I guess a change was made.

    By the way, in "researching" that, I was confused as to whether the RESn pin was actually pulled up by the P2 or not because some posts said (or seemed to me to say) that an external pull-up was necessary. And if that's true and one designed with the opposite assumption, then that'd likely be a problem. So what's the word now that we have actual P2 silicon? Is RESn pulled up by the P2 itself (possibly lightly)? But I think that I read that the P2D2 pulls it up (externally), even if it may not be strictly necessary. Sorry, I didn't carefully and exhaustively read all the related posts. Anyway, good luck figuring your board out.
  • RaymanRayman Posts: 9,805
    edited 2019-11-14 - 23:28:19
    I've assumed that RESn is internally pulled high, but I guess I need to verify that.

    I also noticed that I didn't tie TEST to GND, like they did on Eval Board. But, connecting to ground didn't fix RESn problem...


    Actually, it seems there is an external pull-up on RESn on Eval. Board.
    Prop Info and Apps: http://www.rayslogic.com/
  • jmgjmg Posts: 14,019
    Rayman wrote: »
    I've assumed that RESn is internally pulled high, but I guess I need to verify that.
    I also noticed that I didn't tie TEST to GND, like they did on Eval Board. But, connecting to ground didn't fix RESn problem...
    How strongly does RESn pull to GND ? Do all your VIO have bias ?
    The Eval SCH shows a 10k pullup, but it's not clear if there is an internal pullup. It's common to have pullups on RESn and
  • I think the documentation should include a description of RESn and TEST pins...

    I copied my FTDI reset circuit from a P1 design, but I see that Eval board does it differently. That might be a problem as well...
    Prop Info and Apps: http://www.rayslogic.com/
  • I can pull RESn with a 10k resistor.
    But, maybe I didn't try that and grounding TEST at the same time...
    Prop Info and Apps: http://www.rayslogic.com/
  • VonSzarvasVonSzarvas Posts: 1,661
    edited 2019-11-14 - 23:56:12
    Rayman wrote: »
    I think the documentation should include a description of RESn and TEST pins...

    I copied my FTDI reset circuit from a P1 design, but I see that Eval board does it differently. That might be a problem as well...

    I was just thinking the same. If we could ask @cgracey to confirm what the TEST pin is for, and how it should be connected on user boards, then I'll get that detail added to the Eval docs pinout table. With Eval we have it hooked to Ground, but I can't recall if that could be to either rail (or allowed to float), and if it might have any possible user purpose.

    As for RESn, that would be good to ask Chip's confirmation too, if there's any internal pull resistance and/or capacitance.

    On the Eval, we had RESn pulled up anyway, because the DTR reset circuit requires a pull-up on the P2 side of the series capacitor. I could create a little app-note about the P2 reset and data interface that we used on the Eval board, and get that shared out as a reference. The common P1 reset circuit would also work; the main reason for the new version is that it's simpler.

  • jmgjmg Posts: 14,019
    VonSzarvas wrote: »
    As for RESn, that would be good to ask Chip's confirmation too, if there's any internal pull resistance and/or capacitance.
    IIRC there is a noise filter + schmitt trigger, but not any significant capacitance. (unsure about pullup ?)

    VonSzarvas wrote: »
    On the Eval, we had RESn pulled up anyway, because the DTR reset circuit requires a pull-up on the P2 side of the series capacitor. I could create a little app-note about the P2 reset and data interface that we used on the Eval board, and get that shared out as a reference. The common P1 reset circuit would also work; the main reason for the new version is that it's simpler.
    UB3 P2 reset is even simpler :) - no C, no R, and a clean reset pulse of 100us on every DTR _/= edge.

    A simple 'minimum connection' app note is a good idea.
    That could also include a suggested Xtal CAP value & Osc sources.
    Did Parallax collect Osc MHz values for the first batch of boards ?
    My tests of EvalA, hint that the present chosen Xtal has too low a CL, but that's a sample size of 1.


  • RaymanRayman Posts: 9,805
    edited 2019-11-15 - 00:38:00
    Thanks.

    The other think I'm possibly doing wrong is using the FTDI with 5V I/O and 10k series resistors between it's RX/TX and the Prop's.
    This was a trick to prevent the Prop1 from powering up the FTDI chip and generating a reset pulse.
    But, maybe the FT231X doesn't need that...
    Prop Info and Apps: http://www.rayslogic.com/
  • jmgjmg Posts: 14,019
    Rayman wrote: »
    Thanks.

    The other think I'm possibly doing wrong is using the FTDI with 5V I/O and 10k series resistors between it's RX/TX and the Prop's.
    This was a trick to prevent the Prop1 from powering up the FTDI chip and generating a reset pulse.
    But, maybe the FT231X doesn't need that...

    If you intend to power USB separate from P2, then I think that's still needed.
    IIRC the Eval B adds speed-up parallel caps to those 10k's
  • Peter JakackiPeter Jakacki Posts: 8,725
    edited 2019-11-15 - 02:48:52
    I did up reference schematics and pcb layout early last year as part of doing up a datasheet just so people wouldn't get caught. Guess this is a case of "RTM" :) The link is in bold in my sig but there are many documents there too.

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  • The TEST pin should be tied low. If it goes high, the chip enters ON Semi test mode.

    RESn has no internal pull-up, so you'll need to add one.
  • Thanks
    That might explain it
    Prop Info and Apps: http://www.rayslogic.com/
  • samuellsamuell Posts: 449
    edited 2019-11-15 - 14:36:31
    Easy fix, IMHO, but probably an ugly one. You just have to scrape the ground plane around the TEST pin, and solder bridge it (if there is a ground plane near that pin). As for the RESET pin, probably it will be more complicated, but still doable. Then, you should seize the opportunity to run more tests before you correct the layout.

    Kind regards, Samuel Lourenço
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