Notes and progress for the new 64004-ES Hyper Memory accessory

VonSzarvasVonSzarvas Posts: 1,628
edited 2019-09-23 - 10:27:42 in Propeller 2
Thread to document progress, for members that are experimenting with the new Hyper Memory.

Starting with a reset tip..

You will need to assert IO+15 high to enable the memory module.

IO+15 by default holds the memory chips in reset, so that when inserted they always power-up in a sane cleared state.

This function can be changed by adjusting R204 positions thus:
1. Reset held by 10K to VSS (default setting)
2. Reset controlled by external reset (ie. hook to RESn on the RevB Eval board) 
3. Remove R204 to have module always on.

Check the schematic and docs for full information.

Comments

  • Yes this is IO+15 reset high is good advice

    The other thing to note is the early schematic (that had 27 ohm resistors) had different pin use for P9-12 to the final version
  • Board seems to be different to schematic
    +8 hyperram CK
    +10 Hyperram RWDS
    +12 Hyperram CS
    +9 Hyperflash CK
    +11 Hyperflash RWDS
    +13 Hyperflash CS
    
    Melbourne, Australia
  • Yep, thats the default config.

    The Hyperram is "Hyper A", and the Hyperflash is "Hyper B", since each site could be loaded with either type of memory separately, if the corresponding chip select jumper is changed over. But the default of one of each is good

    By default IO+14 is the interrupt signal, and is connected to Hyper B (Flash) Int signal, I believe
  • Here's a capture of a Hyperram read transaction.
    800 x 600 - 93K
    Melbourne, Australia
  • Looks good!

    Have you been able to measure throughput speed yet?
  • Here's the code I wrote for a HyperRAM test board.
    It requires FastSpin Version 3.9.33 to compile.
    I set up the pins from ozpropdev's screen capture for it being plugged into P32 and up.

    What it is, is a terminal style program for exercising the HyperRAM. It expects capital letters.

    You can press L to change the latency clock setting, from 3 to 6. For performance reasons of course you want 3.
    Choose (F)ixed or (V)ariable latency. Variable isn't supposed to work if it's a dual stack chip.
    The printout of "Transitions" is how many clock transitions it took for RWDS to respond.

    Press (A) to change the command address. Then after entering that you can press (W) to write a value, and (R) to read it back or (B) to burst read it back.
    Read or Burst Read is controlled by (N), number of words to read (1 to 128).

    I'm available for any questions.
    677 x 474 - 43K
    677 x 654 - 45K
  • VonSzarvasVonSzarvas Posts: 1,628
    edited 2019-09-24 - 09:36:06
    Thank you @whicker

    Are you on the RevA or RevB eval?

    Is anyone aware of code changes between the 1st and 2nd version P2 chips ? I mean... will the HyperRAM and HyperFlash code need adjusting between the chip versions; does your code includes instructions that might have changed ?

  • I've got Rev A.
  • VonSzarvas wrote: »
    Is anyone aware of code changes between the 1st and 2nd version P2 chips ? I mean... will the HyperRAM and HyperFlash code need adjusting between the chip versions; does your code includes instructions that might have changed ?
    Off the top of my head: Streamer mode numbers are completely re-encoded, and some have extra functions. The PTRA/B changes could affect tables in hubRAM.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • Thanks @whicker
    Tested on Rev A & B Eval boards with latest Flexgui Ok.
    Melbourne, Australia
Sign In or Register to comment.