New P2 Silicon

1111214161722

Comments

  • evanh wrote: »
    I don't have the skills to give input. The stuff that Saucy posted on filter performance when we were adding SincX filters went straight over my head.

    I think it went through mine, but left little trace.

    Saucy, can you refresh us?

    I think the idea was that rather than dwell on a certain ratio, which creates a dead spot, of sorts, the integrator would always be meandering above and below the midpoint.
  • I did not have any success with 2 RC stages on the P1. Here was the discussion: forums.parallax.com/discussion/comment/1459359/#Comment_1459359
    James https://github.com/SaucySoliton/

    Invention is the Science of Laziness
  • I did not have any success with 2 RC stages on the P1. Here was the discussion: forums.parallax.com/discussion/comment/1459359/#Comment_1459359

    Thanks, Saucy.
  • cgraceycgracey Posts: 11,777
    edited 2019-09-17 - 08:22:17
    I got the scope smart pin mode and SCOPE data pipe documented today.

    Just search for "ADC Scope":

    https://docs.google.com/document/d/1gn6oaT5Ib7CytvlZHacmrSbVBJsD9t_-kmvjd7nUR6o/edit?usp=sharing
  • evanhevanh Posts: 8,112
    edited 2019-09-17 - 10:14:15
    I should start testing the external bitstream feature ...

    Hmm, grr, going back to Pnut is hurting my mental well-being. I like using Eric's #include "more-code.spin2" but I can't rely on it assembling correctly for the revB chips yet. I have all my helper subroutines in one file where any little fixes are naturally carried to all test programs that include that file.
    I love the whooshing sound of deadlines as they fly by.
  • evanh wrote: »
    I should start testing the external bitstream feature ...

    Hmm, grr, going back to Pnut is hurting my mental well-being. I like using Eric's #include "more-code.spin2" but I can't rely on it assembling correctly for the revB chips yet. I have all my helper subroutines in one file where any little fixes are naturally carried to all test programs that include that file.
    me too :(
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
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    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
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  • Chip,
    With the few tricks I've learnt over the past 6 months I find that I can save a few more longs in the SD and Monitor ROM ;)
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • evanh wrote: »
    I should start testing the external bitstream feature ...

    Hmm, grr, going back to Pnut is hurting my mental well-being. I like using Eric's #include "more-code.spin2" but I can't rely on it assembling correctly for the revB chips yet. I have all my helper subroutines in one file where any little fixes are naturally carried to all test programs that include that file.

    If you don't mind being a guinea pig here's a version of fastspin that can compile for the new revB chips. Just pass "-2b" on the command line. To get the original silicon use "-2a". For now plain "-2" is the same as "-2a", but that will change once more of the new silicon is out in the wild.

    I think the only instruction encoding changes are:
    - rdlut/wrlut accept PTRA and PTRB special forms
    - the PTRA/PTRB forms allow offset from -64 to +63 if there is no update specified
    - new instructions setscp and getscp

    AFAICS the other changes are compatible (e.g. the extra bits in drvh/drvl/etc.).

    Did I miss anything?
  • Here's the old list of changes - https://forums.parallax.com/discussion/169282/list-of-changes-in-next-p2-silicon/p1

    Only thing I can see that might be missing is GETCT WC

    I love the whooshing sound of deadlines as they fly by.
  • Oh, I'll be wanting the Linux binary of fastspin please. :)
    I love the whooshing sound of deadlines as they fly by.
  • evanh wrote: »
    Oh, I'll be wanting the Linux binary of fastspin please. :)

    It'll be in the "build" folder of your git repo after you do a "git pull; make" :).

    On the serious side I've pretty much assumed that most Linux users of fastspin are comfortable with (and perhaps even prefer) building it from source. If enough people tell me I'm wrong I can revisit that.
  • Ah, I'd assumed, by the way you presented the zip file, that the changes weren't in Git.
    I love the whooshing sound of deadlines as they fly by.
  • Well, it's working. But then the only new thing I'm using right now is the SINC smartpin mode.
    I love the whooshing sound of deadlines as they fly by.
  • ersmith wrote: »
    evanh wrote: »
    I should start testing the external bitstream feature ...

    Hmm, grr, going back to Pnut is hurting my mental well-being. I like using Eric's #include "more-code.spin2" but I can't rely on it assembling correctly for the revB chips yet. I have all my helper subroutines in one file where any little fixes are naturally carried to all test programs that include that file.

    If you don't mind being a guinea pig here's a version of fastspin that can compile for the new revB chips. Just pass "-2b" on the command line. To get the original silicon use "-2a". For now plain "-2" is the same as "-2a", but that will change once more of the new silicon is out in the wild.

    I think the only instruction encoding changes are:
    - rdlut/wrlut accept PTRA and PTRB special forms
    - the PTRA/PTRB forms allow offset from -64 to +63 if there is no update specified
    - new instructions setscp and getscp

    AFAICS the other changes are compatible (e.g. the extra bits in drvh/drvl/etc.).

    Did I miss anything?

    Eric, the PTRA/B non-updating offset range is -32 to +31. Look at the latest Google doc for the exact encoding. Otherwise, your list of instruction encoding changes is correct.
  • Hi Chip,

    Will this revision be available on an Eval board for us early adopters, or will we have to wait for the finished product? If so, when will it be available? (sorry if I missed the information somewhere in all threads)

    /Johannes
    SIDcog - The sound of the Commodore 64 in a single cog: Thread, OBEX
  • Ahle2 wrote: »
    Hi Chip,

    Will this revision be available on an Eval board for us early adopters, or will we have to wait for the finished product? If so, when will it be available? (sorry if I missed the information somewhere in all threads)

    /Johannes

    Johannes, as soon as we get more chips, we will make new P2 Eval boards with them. We are expecting over 1,000 new chips. Waiting for ON Semi to find out the delivery date.
  • An earlier expected delivery date got a little delayed with the testing hiccup.
    I love the whooshing sound of deadlines as they fly by.
  • cgracey wrote: »
    ...as soon as we get more chips, we will make new P2 Eval boards with them. We are expecting over 1,000 new chips. Waiting for ON Semi to find out the delivery date.
    Where/how do I register interest in such a board?
  • cgracey wrote: »
    ...as soon as we get more chips, we will make new P2 Eval boards with them. We are expecting over 1,000 new chips. Waiting for ON Semi to find out the delivery date.
    Where/how do I register interest in such a board?

    If you want one, there will be plenty available.
  • Chip: Any update on getting more P2 chips packaged and eval boards made?
  • David Betz wrote: »
    Chip: Any update on getting more P2 chips packaged and eval boards made?

    Yes, we are supposed to receive at least 1,000 chips on October 18th. We are scheduled to make 192 P2 Eval boards then.
  • cgracey wrote: »
    David Betz wrote: »
    Chip: Any update on getting more P2 chips packaged and eval boards made?

    Yes, we are supposed to receive at least 1,000 chips on October 18th. We are scheduled to make 192 P2 Eval boards then.
    October 18? That's my birthday! :smile:

  • Is that enough chips to also sell chips without the ES board?
    Prop Info and Apps: http://www.rayslogic.com/
  • SeairthSeairth Posts: 2,392
    edited 2019-09-26 - 23:22:21
    More importantly, can we start giving you our money now???
  • jmgjmg Posts: 14,027
    cgracey wrote: »
    Yes, we are supposed to receive at least 1,000 chips on October 18th. We are scheduled to make 192 P2 Eval boards then.
    Will those be 100% OnSemi tested, and what 'stress voltage' test levels are they now using ?
  • Rayman wrote: »
    Is that enough chips to also sell chips without the ES board?

    Yes.
  • jmg wrote: »
    cgracey wrote: »
    Yes, we are supposed to receive at least 1,000 chips on October 18th. We are scheduled to make 192 P2 Eval boards then.
    Will those be 100% OnSemi tested, and what 'stress voltage' test levels are they now using ?

    They will pass ON's digital tests and Parallax' analog pin tests. No V-stress test will be applied.
  • Yeah! Time to start work on my dream P2 board...
    Prop Info and Apps: http://www.rayslogic.com/
  • I really like the time is coming to start the next generation of work. In the mean time I like to watch others playing with words. So if iirc there are some links between the propeller 1 and Finland. So we have a finish propeller 1 and an almost finished propeller 2. So funny.
    no reason to reason if you feel feelings: in love with the propeller

    How-2-TACHYON
  • ErNa wrote: »
    I really like the time is coming to start the next generation of work. In the mean time I like to watch others playing with words. So if iirc there are some links between the propeller 1 and Finland. So we have a finish propeller 1 and an almost finished propeller 2. So funny.

    Oh sh.. does Ken knows that? He need to send you a P2 to finally get it finished!

    Enjoy!

    Mike
    I am just another Code Monkey.
    A determined coder can write COBOL programs in any language. -- Author unknown.
    Press any key to continue, any other key to quit

    The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this post are to be interpreted as described in RFC 2119.
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