New P2 Silicon

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  • jmgjmg Posts: 13,902
    cgracey wrote: »
    Look at the plots below for old and new silicon. When VIO (all VIO's) rises on the new part, current remains directly proportional to voltage, even from 0V, so there's some resistor present that shouldn't be there. If this were an active component problem, we'd need to get to at least 300mV before we'd see any conduction. This happens from 0V.
    Interesting graphs. The abrupt rise you question, looks a normal i = C*dV/dT effect of decoupling + die capacitance.
    The tails are interesting.
    As VDD ramps, VIO current goes slightly negative, and VDD current plateaus ~ 20mA, until VIO ramps past ~ 1V - so there are slight interactions between VDD & VIO ?

    Maybe VDD has some injection effect/path to VIO, and VIO needs to be pulled actively to 0V to fight that (hence -ve current, from an active power supply).
    That would explain why the residual VDD current goes away when VIO ramps.
    When I checked a single VIO on P2ES1, there was no current injection seen ?

  • jmgjmg Posts: 13,902
    cgracey wrote: »
    At this point, there's no point in me going out to Pocatello where the testing is being done.
    Not if this is a baked-in die issue.
    Tho earlier indications were that parts that failed this way on test, were subsequently OK on a Board ?
    How many packaged parts do OnSemi have - maybe they can send all the current parts, tagged as 'tested ok' / 'tested Icc=XXX' / 'not tested yet'
    Did ANY of the first ES1 batch get rejected for this reason ? Maybe the issue is not brand new ?
  • jmg said what I was thinking, but that 10~22mA leakage from VDD to VIO was present on P2ES1 as well.

    It makes me wonder though, whether that leakage damages something (level translators? that happen to be more brittle on P2ES2 compared with P2ES1), that results in the 'ohmic' behaviour later. Is there a good reason to bring the power supplies up in the order that they are? Could they bring them up concurrently?

  • jmgjmg Posts: 13,902
    edited 2019-08-15 - 05:12:43
    Tubular wrote: »
    jmg said what I was thinking, but that 10~22mA leakage from VDD to VIO was present on P2ES1 as well.

    It makes me wonder though, whether that leakage damages something (level translators? that happen to be more brittle on P2ES2 compared with P2ES1), that results in the 'ohmic' behaviour later. Is there a good reason to bring the power supplies up in the order that they are? Could they bring them up concurrently?
    Yes, it's worth checking where that current flows, to see the power density.
    When I checked a std IO before I got ~0mA, a quick measure on a ES1, seems to show 10mA can flow out of V2431, which I think is the PLL section, so there may be more VDD-VIO cross-coupling going on in that zone.
    All other VIO pins show ~0mA of lateral currents. (VIO = 0V)

  • Ok thats a really good test. Yes the PLL was on 28~31.
  • cgracey wrote: »
    That's about what kind of time I'm looking at, if I drove. I don't know if I trust my '97 Altima to make that trip, though.

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  • I need to simulate to learn why VIO current flows to GND when VDD is at 1.8V and VIO is held at GND. That doesn't make immediate sense to me.
  • jmg wrote: »
    Did ANY of the first ES1 batch get rejected for this reason ? Maybe the issue is not brand new ?

    There was an ES1 packaged chip (final, not globtop) here that arrived with one of the VIOs in the 56-63 range "shorted". It's on an Eval rev A board, and rendered that board useless for programming.

    Interestingly that board did pass some quick tests (including programming) at Parallax mfg, before shipping.

    Would there be any useful tests or measurements to make on that chip?

    I'll go dig it out and measure the resistance at each VIO pin to GND and VDD.
  • jmgjmg Posts: 13,902
    VonSzarvas wrote: »
    Would there be any useful tests or measurements to make on that chip?
    I'll go dig it out and measure the resistance at each VIO pin to GND and VDD.
    You could check the order of the 'short' to see if it is in the same ball park of current Chip shows above ( 5 ohms).
    You could also check the injection current at V2431, ie mA meter to GND, VDD present
    VonSzarvas wrote: »
    There was an ES1 packaged chip (final, not globtop) here that arrived with one of the VIOs in the 56-63 range "shorted". It's on an Eval rev A board, and rendered that board useless for programming.
    Interestingly that board did pass some quick tests (including programming) at Parallax mfg, before shipping.
    So you mean it initially seemed to work OK, but then failed, in the field ?

  • VonSzarvas wrote: »
    jmg wrote: »
    Did ANY of the first ES1 batch get rejected for this reason ? Maybe the issue is not brand new ?

    There was an ES1 packaged chip (final, not globtop) here that arrived with one of the VIOs in the 56-63 range "shorted". It's on an Eval rev A board, and rendered that board useless for programming.

    Interestingly that board did pass some quick tests (including programming) at Parallax mfg, before shipping.

    Would there be any useful tests or measurements to make on that chip?

    I'll go dig it out and measure the resistance at each VIO pin to GND and VDD.

    That would be good. There may be an issue with getting proper polarity on your ohm meter, so you aren't just measuring the clamp doide. You'll want to measure so that VIO gets the positive voltage and GND gets the negative voltage.
  • I’ve skimmed reading the problem. I can’t think of anything atm although much of this is out of my league. Unfortunately i cannot test anything for you Chip as I’m still in the UK and wont be home for another 2 weeks.

    Is there any relationship for the failed parts vs where they are on the wafer. IIRC it was usual to have a die mark for each die on the wafer. Does this still happen?

    It will be interesting to see if any of these untested dies fail when packaged.

    And interesting to see the P2EVAL results too.
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  • samuellsamuell Posts: 405
    edited 2019-08-15 - 11:45:12
    This is a very big setback. Did ON Semi changed anything in the IO banks? Or is it the fab process that got messed up? ONC18 is not a bleeding edge process and this shouldn't happen.

    I would buy one of these boards, if only one or two banks were scrapped. I'm interested in the processing power more than anything else.

    Kind regards, Samuel Lourenço
  • jmg wrote: »
    So you mean it initially seemed to work OK, but then failed, in the field ?

    Correct.

    V5659 was the bad pin.
    Just measured with a 4-wire resistance meter and got 1.014 ohm.


    From notes I can see @evanh had a similar issue (VIO short) on V2431 when he got the RevA Eval board. I think it was since replaced or repaired, so that may not be available for measuring.




  • I wonder if you can stack eval boards and use one to verify the one under test works...
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  • Is it possible that during the packaging process, the wafers were rotated 90, 180, or 270 degrees? Just throwing that out there. Probably not likely.
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  • ke4pjw wrote: »
    Is it possible that during the packaging process, the wafers were rotated 90, 180, or 270 degrees? Just throwing that out there. Probably not likely.

    I believe these tests were done on the die and not packaged products. Good call nonetheless.
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  • jmgjmg Posts: 13,902
    VonSzarvas wrote: »
    jmg wrote: »
    So you mean it initially seemed to work OK, but then failed, in the field ?

    Correct.
    V5659 was the bad pin.
    Just measured with a 4-wire resistance meter and got 1.014 ohm.
    From notes I can see @evanh had a similar issue (VIO short) on V2431 when he got the RevA Eval board. I think it was since replaced or repaired, so that may not be available for measuring.
    Ah, ok. Field failures are not quite the same effect.

    I wonder has Chip checked ALL of the packaged P2-ES2s he has ?

  • jmg wrote: »
    VonSzarvas wrote: »
    jmg wrote: »
    So you mean it initially seemed to work OK, but then failed, in the field ?

    Correct.
    V5659 was the bad pin.
    Just measured with a 4-wire resistance meter and got 1.014 ohm.
    From notes I can see @evanh had a similar issue (VIO short) on V2431 when he got the RevA Eval board. I think it was since replaced or repaired, so that may not be available for measuring.
    Ah, ok. Field failures are not quite the same effect.

    I wonder has Chip checked ALL of the packaged P2-ES2s he has ?

    We just did that. See the "need your help" thread.

    These glob-tops all have lousy wire bonds on the leadframe side. There was some epoxy/contamination left on those leads and they didn't ultrasonically weld very well. This is another problem we have, but it's certainly not a design problem.
  • SaucySolitonSaucySoliton Posts: 247
    edited 2019-08-19 - 04:48:45
    cgracey wrote: »
    Here is a plot of total VIO current during the test suite.

    Note that there's a base current of ~125mA that shouldn't be there. Also, the test starts off at -22mA, which is weird.
    The die should be rejected right there. Even if it's functional, we want the leakage to be low for power efficiency.


    P2_VIO_Test_Current.png
    The IO test takes the last ~45% of test time. We don't have a time scale for this image. Also don't know if this is the high current or low current IO test.

    Heating takes current and time. So a probe could burn during the IO test as a result of the base current.

    The damage could be cumulative. If the probe looses a tiny bit of length from nearly melting, the contact pressure will be reduced. Which increases resistance and results in more heating the next time. It's a possible explanation why the probe lasted one wafer and failed on the second.

    It's also possible that the probes could handle the current for one die, but quickly repeated high current results in destruction.
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  • And if I understand correctly, the current spikes running through resistance, create squared power, so the spike will heat up the resistor what will result in thermal expansion. I once could see the temperature rise of a FET chip when PWM-ing. The silicon heats very quickly locally and heat transfer to the environment is delayed, so you can only measure an average temperature. So that's plausible that the probe degrades quickly.
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  • I posted a link to the new silicon instruction spreadsheet at the top of this thread.

    Here it is:

    https://docs.google.com/spreadsheets/d/1_vJk-Ad569UMwgXTKTdfJkHYHpc1rZwxB-DcIiAZNdk/edit?usp=sharing

    - The BITx/WxPIN/DIRx/OUTx/FLTx/DRVx instructions changed to accommodate the bit/pin adder in the 5 bits above the base bit/pin value.

    - RDLUT/WRLUT now accept PTRx expressions.

    - POP WZ now returns Z=1 for popped value == 0.

    - GETCT WC added for reading the upper 32 bits of CT.

    - New SETSCP/GETSCP instructions added.

    - A new column was added to show which instructions shield the next instruction from interruption (ALTx/SCA/etc.).
  • I've been getting back to the documentation for the new silicon. I also added this to the top post in this thread.

    NEW SILICON DOCUMENTATION:

    https://docs.google.com/document/d/1gn6oaT5Ib7CytvlZHacmrSbVBJsD9t_-kmvjd7nUR6o/edit?usp=sharing

    The new parts or changes have a light-red background, so they are easy to spot.

    I've got the new smart pin modes covered, except for the SCOPE mode, which I'll get to next.

    I started working on the streamer section, but have more work to do.

    The PTRx encodings have been updated to accommodate the expanded index and offset values.
  • So bad news is also good news. Great.

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  • Oh cool!! Externally clocked ADC bitstream smartpin mode! You kept that one quiet Chip. :)
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • evanh wrote: »
    Oh cool!! Externally clocked ADC bitstream smartpin mode! You kept that one quiet Chip. :)

    What? I missed that too. Have too look,

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  • evanh wrote: »
    Oh cool!! Externally clocked ADC bitstream smartpin mode! You kept that one quiet Chip. :)

    No, Jmg insisted it be there. It's just never been tested with an external ADC.
  • I've got an AD7400 to test it with. I've previously just asynchronously oversampled to sysclock and that worked. This will be lower power operation at the very least.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • And, btw, that's a second order modulator too if you want me to compare differences in some fashion.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • evanh wrote: »
    And, btw, that's a second order modulator too if you want me to compare differences in some fashion.

    Oh, a 2nd-order modulator. I've been curious about those. I can't figure out if one could be built by adding an effective RC stage to our current integrator.
  • I don't have the skills to give input. The stuff that Saucy posted on filter performance when we were adding SincX filters went straight over my head.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
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