ON Semi figured out the VIO problem!!!!

1235»

Comments

  • evanhevanh Posts: 7,938
    edited 2019-09-10 - 12:21:17
    From that, it does look like 5 Volts is okay. But temperature will affect it too.

    EDIT: Oh, wow, temperature has a huge impact. I got a whole milliamp at 5 Volts when at 1 °C. It doesn't drop below 1 microamp until below 3.3 Volts, and that was at 4 °C by then. So negative temperatures are going to draw extra power at 3.3 Volts.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • evanh wrote: »
    From that, it does look like 5 Volts is okay. But temperature will affect it too.

    EDIT: Oh, wow, temperature has a huge impact. I got a whole milliamp at 5 Volts when at 1 °C. It doesn't drop below 1 microamp until below 3.3 Volts, and that was at 4 °C by then. So negative temperatures are going to draw extra power at 3.3 Volts.

    I wonder why you can get to 6V, but they were often getting latch-up at 4.6V. The more times they tested a given chip, the more likely it would develop the latch up failure.
  • samuellsamuell Posts: 409
    edited 2019-09-10 - 15:41:22
    evanh wrote: »
    It's probably unwise to have a deployed operating voltage that high.

    Here's a graph of my earlier measurements with an extrapolation in brown. I'm not sure what would be considered as a base quiescent current, I'm guessing by the beginnings of a levelling out at the left there that some decent fraction of 1.0 uA would be it.
    Screenshot_20190910_202258.png
    When I saw that, I was astonished! You tested way beyond 6V!? Have you done this tests with the Vcore powered or unpowered?

    Anyway, having learned that, it is no wonder that I didn't ruined my P2 when I "brushed" 5V into one of the VIO pins.

    Kind regards, Samuel Lourenço
  • cgracey wrote: »
    evanh wrote: »
    From that, it does look like 5 Volts is okay. But temperature will affect it too.

    EDIT: Oh, wow, temperature has a huge impact. I got a whole milliamp at 5 Volts when at 1 °C. It doesn't drop below 1 microamp until below 3.3 Volts, and that was at 4 °C by then. So negative temperatures are going to draw extra power at 3.3 Volts.

    I wonder why you can get to 6V, but they were often getting latch-up at 4.6V. The more times they tested a given chip, the more likely it would develop the latch up failure.

    Series resistor and capacitance control the rise rate and peaks ?
  • samuell wrote: »
    When I saw that, I was astonished! You tested way beyond 6V!? Have you done this tests with the Vcore powered or unpowered?
    Hehe, yeah, I was a little nervous myself. It's funny, I kept thinking I'd gone far enough and then I'd come back and go, why not push further. After al, how could it hurt with the current so small.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • cgracey wrote: »
    I wonder why you can get to 6V, but they were often getting latch-up at 4.6V. The more times they tested a given chip, the more likely it would develop the latch up failure.
    I've not cycled all that many times. Above 5 Volts, maybe 20 times on V4855 and probably only about 5 times for V4047.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • evanhevanh Posts: 7,938
    edited 2019-09-11 - 11:42:21
    samuell wrote: »
    Have you done this tests with the Vcore powered or unpowered?
    Oops, missed that question on first reading. Both. Those measurements were made with VDD = 0.0 Volts but I later rechecked the VIO = 6.8 Volts with VDD = 3.3 1.8 Volts. Current draw didn't change.

    EDIT: 1.8 V correction
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • jmgjmg Posts: 13,937
    evanh wrote: »
    samuell wrote: »
    When I saw that, I was astonished! You tested way beyond 6V!? Have you done this tests with the Vcore powered or unpowered?
    Hehe, yeah, I was a little nervous myself. It's funny, I kept thinking I'd gone far enough and then I'd come back and go, why not push further. After al, how could it hurt with the current so small.
    One failure mechanism could be when the scr fires, discharges CD, and the peak current damages locally.
  • evanh wrote: »
    samuell wrote: »
    Have you done this tests with the Vcore powered or unpowered?
    Oops, missed that question on first reading. Both. Those measurements were made with VDD = 0.0 Volts but I later rechecked the VIO = 6.8 Volts with VDD = 3.3 Volts. Current draw didn't change.

    VDD seems high at 3.3 if P2 core is consuming much current.

    Some early notes put safe VDD maximum at 2.2V, and VIO at 4V without current limiting.

    Just mentioning in-case relevant to interpreting your results, and the over voltage behaviour.
  • Sorry, wasn't thinking when I wrote that. I powered it up with the built-in Eval board regulators so 1.8 Volts was what was used of course. The V4855 VIO jumper was removed to power separately.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • jmg wrote: »
    One failure mechanism could be when the scr fires, discharges CD, and the peak current damages locally.
    I would've been happy to see that happen. On the other hand it would've annoyed me to miss it.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • On the new P2 Eval boards, there is only one jumper which feeds 5V to all the local 3.3V LDO's.

    Von Szarvas, you had said something earlier about what must be done to drive voltage onto the LDO outputs, so that Evanh will be able to continue his experiments. What was it?
  • I'm guessing desolder an LDO then put power on its I/O header. That's doable.

    On that note I might try pulling these two capacitors off this board I've already got first. Job for tomorrow maybe.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • cgracey wrote: »
    On the new P2 Eval boards, there is only one jumper which feeds 5V to all the local 3.3V LDO's.

    Von Szarvas, you had said something earlier about what must be done to drive voltage onto the LDO outputs, so that Evanh will be able to continue his experiments. What was it?

    For voltage only testing (ie. not sourcing much current from any VIO's), then you could remove the LDO Vin jumper and instead feed voltage (max 6V) in from one of the edge header Vxxxx pins. That VIO group will see the voltage applied, and all other VIOs will get 3V3 via their own regulators.

    "much current" - Datasheet for the LDO not to hand, but assume <50mA is OK.



    Caveat- we don't recommend this at all! Not supported, not warrantied use case. Proceed at user risk! That agreed, with usual care, will allow over voltage injection. Damage to injected LDO or P2 likely if current sourced by any VIO group excessive.
  • I hear ya there Von. Reversing flow on a linear regulator is not a good thing to do.

    Also, I note, on that part, the EN input needs to be high first, otherwise the LDO will attempt to hold its output low.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • yeah, but there's also an internal reverse biased diode that will pull EN high once Vout exceeds about 1V, and shunt the output fet on.
  • cgracey wrote: »
    I got a call today from the engineering boss at On Semi and he said they now realize what's triggering the latch-up destruction on VIO pins.

    Their test technician, who Wendy and I have been working with, realized yesterday that in the test suite for the new silicon, an additional test had been added that wasn't (but should have been) in the test suite for the original silicon. It's a V-stress test which raises VDD and VIO voltages 40% above 1.8V and 3.3V. This is what's been blowing out the VIO pins!!! This indicates that there is some design weakness in the chip regarding latch-up immunity at higher voltages, which may incidentally occur in a customer application.

    This is funny, because Wendy and I had asked in a dozen different ways if ANYTHING had changed in the test suite, aside from the updated digital test patterns, and the answer was always "no", to paraphrase. It just wasn't making sense, but the tester seemed to play a role. Anyway, the tester WAS blowing up the chips.

    I'm relieved that we now know what the trouble is, but it's frustrating to have lost a month diagnosing this problem, and even more so that this V-stress test wasn't applied to the first-version silicon, as it would have resulted in awareness of a problem that would have been already fixed in this new silicon. The fix is just placing guard rings around several N-wells, which is no big deal. At this point, though, it means new masks and a wafer run.

    So, they are going to be able to package us up a few hundred new chips in the Amkor package. It will take a few weeks, at least. We will be able to build new P2 Eval boards immediately. They had tested two wafers out of six, before stopping after both probe cards had sustained damage to VIO pins. Many of those dies are now toast. They will need to re-probe those wafers, checking for excessive VIO current, or just probe virgin wafers which haven't been exposed to the V-Stress test, in order to get dies to send to Amkor for packaging.

    I'm really glad that we know what the problem is now.

    Yea, thats really screwed up. THEY screwed up and left a test out, which should have found the problem so it would be fixed already, now you have to pay to fix what should have been found and fixed during the first iteration.

    Particularly patient proactive practice positively predicates practically precise poly-processor Parallax Propeller programming paradigms.

    .
  • Cluso99 wrote: »
    Oh, at last the problem has been found :smiley:
    It’s a bit embarrassing for ON. Hopefully they’ll push the fixes thru quickly.
    Meanwhile you can get some more chips/boards out into more hands.

    Honestly, I think it might be prudent to get those devices out to people to test in a more realistic environment before the fixes get locked in, thus providing an opportunity to hit the brakes and fix any serious issues that might show up, however unlikely that is to happen.
    Particularly patient proactive practice positively predicates practically precise poly-processor Parallax Propeller programming paradigms.

    .
  • Great stuff. Congratulations @cgracey
    “Light thinks it travels faster than anything but it is wrong. No matter how fast light travels, it finds the darkness has always got there first, and is waiting for it.”
    “You only live twice:
    Once when you are born
    And once when you look death in the face”
Sign In or Register to comment.