Automated Testing of P2's

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  • jmgjmg Posts: 14,135
    edited 2019-08-31 - 20:14:48
    Attached are some Power supply rise plots, of the P2Eval, powered into P2_USB side, (not FT231x side) from either a Li USB Power PAK, or a PC USB port.
    5V is measured on a header pin.

    VIO seems to be non monotonic, and I also notice VDD is a bit cleaner on the USB Pak, than on the PC_USB, even tho the 5V ramps and 3v3 are fairly similar

    The plot of VLDO and VIO is interesting, shows if VIO is jumpered to a LDO, then VIO would be applied ~ 750us before Vdd has reached 1v8.
    Not sure what that means about pin reset states ?
    (edited to clarify connections)
  • Some nice high-res sampling there. The PC-USB powered supply will have an alternative reference path to your sampling device, creating some minor ground loop. This shows up in the slightly raised and rough traces starting around -2000 us for the PC-USB cases.
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  • evanhevanh Posts: 8,365
    edited 2019-08-31 - 12:00:53
    Regarding the Eval board's PC-USB behaviour, where are you taking the voltage measurement from? The USB socket side of the PTC (F401) will look a lot cleaner than the FT231 side. That PTC adds a lot of resistance.

    EDIT: So, what you're seeing there on the 3v3 rail is probably the USB automatics cutting the power momentarily due to low supply voltage at the FT231. This is fixed on the rev2 boards.

    If you use the P2-USB (AUX) socket for power then it should be a lot cleaner.
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  • evanhevanh Posts: 8,365
    edited 2019-08-31 - 15:10:04
    Hmm, my 3.3v VIO switchmode regulator seems to be busted. I haven't used it for ages but it's dead at the moment anyway. Err, it's working now. Maybe it needed a load or maybe I just messed up.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • evanhevanh Posts: 8,365
    edited 2019-08-31 - 15:28:54
    Okay, the USB power switch on my PC-USB supply is disabled due to the AUX USB power switch blowing up some time back, so I can't show that one as a power source.

    Here's one for a bench top linear supplying 5 volts to the AUX input. (Blue is the Common_5v, Orange is the 3.3v VIO switchmode with six of the eight VIO jumpers set, Pink is the 1.8v VDD)
    benchtop.PNG


    This one is P2-USB (AUX) USB socket supplied from a powered hub with on/off switches per port.
    P2-USB.PNG


    And same but zoomed in. (The white noise is from 1 volt/div analogue front end of the scope)
    P2-USB%20x10.PNG
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    640 x 480 - 8K
    640 x 480 - 9K
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  • "... peers into the actual workings of a quantum jump for the first time. The results reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view —the jumps are neither abrupt nor as random as previously thought."
    Were do you cite that from?

    no reason to reason if you feel feelings: in love with the propeller

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  • evanhevanh Posts: 8,365
    edited 2019-08-31 - 15:53:00
    An article posting on Slashdot. Copied from a consumer news site, so it's a journalists take on a newly published paper at the time. Can't remember which one off the top of my head. The whole quote talked about being able to observe a jump building over time and also then intervening to stop it from ever happening.

    EDIT: Here we go - https://science.slashdot.org/story/19/06/03/2151213/physicists-can-predict-the-jumps-of-schrodingers-cat-and-finally-save-it

    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • When it comes to building a model, you always have to make it closed. If a paradox is the result of an experiment, based on a model, you know, your model is not self contained. Imagine to have a switch, made by two conductors facing two metal plates connected to an ideal voltage source of 1 Volt. Ideal means: no inner resistance, can source infinite current. Now you try to close the switch. This switch, in open condition, forms a capacitor having a capacity C, carrying charge, that means: there is energy 1/2 C stored. Now, as the switch closes, the distance one moment is haved, the capacity doubled and so the energy stored. That happens every time, the distance is reduced to 1/2 so in the end, the capacity is growing to infinite and with that the energy stored. The moment the switch closes, the voltage must be zero and the energy, an infinite amount of energy, just is gone.
    This is true also, if the switch is not formed by metal plates, but if in a chunk of silicon there are two conducting areas separated by a non conducting zone. Whenever this zone is reduced, means, the switch is closed, power is dissipated. Even if the switch is made from supra conductors. Conclusion: a lossless switch is not thinkable.
    no reason to reason if you feel feelings: in love with the propeller

    How-2-TACHYON
  • Why is lossless the topic?
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • ErNaErNa Posts: 1,297
    edited 2019-08-31 - 17:28:55
    It's not. ;-) It's just that there is a strange mechanism leading to misconduct and I wanted to point to the fact, that simplification must have limits. The topic is: can a goal be reached. If there is a topic at all. ;-)

    Ok. Took a glance to the link you gave: yes, there is nothing new about the research, if you strip the modern equipment. Schroedingers cat is just an incomplete thought experiment and it is a pity, that so many work is referred to that. Populism in physics, so to say. Quantum jumps were never seen as abrupt or random, there was just no model to describe what a quantum jump is.

    But were are all seeing and actively taking part in a quantum jump P1->P2
    no reason to reason if you feel feelings: in love with the propeller

    How-2-TACHYON
  • jmgjmg Posts: 14,135
    evanh wrote: »
    If you use the P2-USB (AUX) socket for power then it should be a lot cleaner.
    It connects to the P2_USB side. (not the FT231x side)
    evanh wrote: »
    Here's one for a bench top linear supplying 5 volts to the AUX input. (Blue is the Common_5v, Orange is the 3.3v VIO switchmode with six of the eight VIO jumpers set, Pink is the 1.8v VDD)
    Interesting how different these are.
    Even your 1v8 here has a step, and for quite a long time, and 3v3 has 2 steps
    3v3 steps may be due to some UVLO effect where the 5V dips slightly due to the dV/dT loads.
  • ErNa wrote: »
    But were are all seeing and actively taking part in a quantum jump P1->P2

    Then the jumps are abrupt and as random as previously thought

    Mike

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  • evanhevanh Posts: 8,365
    edited 2019-09-01 - 00:03:40
    jmg wrote: »
    Even your 1v8 here has a step, and for quite a long time, and 3v3 has 2 steps
    3v3 steps may be due to some UVLO effect where the 5V dips slightly due to the dV/dT loads.
    Yeah, there'll be an under voltage buck limit. Once hit, any drop in the input voltage will be mirrored in the output. Probably is a lock-out until hysteresis is cleared.

    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • I wish I knew what the problem is with the new silicon. For the first time in this whole project, I feel like there's nothing I can do to push through the impediment that is in the way.

    It seems like it is in ON Semi's hands, only. I am currently out of ideas. In our last meeting, ON said that they were not so sure, after all, what the trouble is. It does seem like latch-up, but their confidence in their initial theory seemed to have dimished.
  • cgracey wrote: »
    I wish I knew what the problem is with the new silicon. For the first time in this whole project, I feel like there's nothing I can do to push through the impediment that is in the way.

    It seems like it is in ON Semi's hands, only. I am currently out of ideas. In our last meeting, ON said that they were not so sure, after all, what the trouble is. It does seem like latch-up, but their confidence in their initial theory seemed to have dimished.

    We feel your pain Chip!
    Hopefully someone soon has a "light bulb" moment and the issue is solved.
    Hang in there buddy. :)
    Melbourne, Australia
  • cgracey wrote: »
    I wish I knew what the problem is with the new silicon. For the first time in this whole project, I feel like there's nothing I can do to push through the impediment that is in the way.

    It seems like it is in ON Semi's hands, only. I am currently out of ideas. In our last meeting, ON said that they were not so sure, after all, what the trouble is. It does seem like latch-up, but their confidence in their initial theory seemed to have dimished.

    Have they established for certain that there is a silicon issue, and that it's not just a test-jig short/failure ? I might have missed it, but it seems the simplest failure point was never fully investigated, and that by proceeding with the tests with a current limited supply you may be able to draw some new conclusions.

    Maybe if the jig was stressing or damaging most all parts, and some more than others, which might explain the "randomness" of the failures thus far? Seems possible that one of those very fine test fingers could have been shorting something at a certain point of depression or during insertion, especially once electrically deformed, if not mechanically.

    I think you mentioned already that ON Semi are intending to proceed with 70mA testing, so hopefully this line of inquiry will bear some results next week.
  • Von,
    I'm of the opinion that we've had the same flaw triggering with the v1 chips when treated a little rough in the Eval boards. I doubt that was caused by ON Semi's tester.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • jmgjmg Posts: 14,135
    cgracey wrote: »
    I wish I knew what the problem is with the new silicon. For the first time in this whole project, I feel like there's nothing I can do to push through the impediment that is in the way.
    It seems like it is in ON Semi's hands, only. I am currently out of ideas. In our last meeting, ON said that they were not so sure, after all, what the trouble is. It does seem like latch-up, but their confidence in their initial theory seemed to have dimished.
    If you can stimulate/ cause a trigger event, if might help quantify this. ?

    Attached is a rough test sweep for a low gain, lateral SCR, which shows the mechanisms of trigger (I3) voltage collapse (VN) and holding/release curent (I6).
    This for a negative inject, but the same plots result from a positive side inject too.

    Shows the trigger/SCR fire current, and the release current, as here I sweep the Vin to reduce the SCR current to finally below holding Current/voltage.

    In a real IC test, the supply current must be limited to prevent damage when triggered.

    I'm not sure if large supply caps have enough energy stored, to damage a triggered part ?
    In an earlier post, Nuvoton spec > 400mA and Atmel spec > 200mA for their Latch-up current tolerances.
    FWIR of testing Atmel parts, we needed ~ 750mA of inject current (not easy to do..), and holding current was < 10mA

    Maybe test the 'good VIO pins' on the part with a failed VIO node, as that might suggest a 'sensitive' or lower level of trigger ?
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  • jmgjmg Posts: 14,135
    edited 2019-09-02 - 02:47:30
    I started with an external function generator sim, simple skewed triangle, and then improved that to work with a 3v3 drive, which is getting low, but that level allows P2 to generate the test ramps
    Here I changed the CAP to change the injection current peak, but you can also change the slopes of the ramps, given I=C*dV/dT
    These SCHs should allow a P2 to self-test across a wide range of Latch-Up injection currents, with the appropriate DAC drive software, and simple NPN+PNP+Stky+CAP- no other supplies needed.

    NPN+PNP+Cap inject into a chosen VIO, driven from any other good VIO in DAC mode.

    Edit: Spotted typo in Pos sim runs..fixed.
  • cgraceycgracey Posts: 11,946
    edited 2019-09-02 - 07:22:09
    Thanks, Jmg. I wonder if this would address the issue.

    From what ON was saying, the latch-up triggers without any external provocation.

    I think your test would allow us to determine the latch-up current threshold, right?
  • jmgjmg Posts: 14,135
    cgracey wrote: »
    Thanks, Jmg. I wonder if this would address the issue.

    From what ON was saying, the latch-up triggers without any external provocation.

    I think your test would allow us to determine the latch-up current threshold, right?

    Yes, it allows controlled 'outside the rails' injection currents, down to under 10mA if you want, to test latch-up thresholds.
    If OnSemi thinks it could be wafer-position sensitive, then a part with a failed VIO could indicate a sensitive location. - so that could be a good one to start with.

    To me, a SCR always needs some provocation to trigger, so this should quantify 'how much'.


    Did you send a couple ES2's to Peter & mount the remaining ones, to check some power cycles ?
    The supply captures I did above, show the real PCBs are not quite the same as their test cases.
    Our captures above show some variances with Power PAKs , HUBS, and PC-USB ports.
  • Rayman wrote: »
    "substrate resistivity, which varies by ... location on the wafer."

    Is this a real thing? I think they might have made this part up...

    Virtually nothing is exact or perfect. Especially something that is mass produced. It's ALWAYS made "just good enough" The resistivity of a wafer is no different. There's a specification. It will vary by location in the bulk silicon the wafer was cut from, and thus vary wafer to wafer and location to location on that wafer. That does not require any specific knowledge of the particulars to state as fact. The question the is not if it varies, but by how much and whether it's enough to matter.
    Particularly patient proactive practice positively predicates practically precise poly-processor Parallax Propeller programming paradigms.

    .
  • Your tests are for an SCR with a parasitic NPN and PNP ... THAT is what you would have if the PMOS transistor was not being used as a capacitor. Since the PMOS has it's S&D shorted, the parasitic circuit is no longer an SCR (similar, but not quite an SCR). I would need to map out the parasitics to determine exactly what you have, but from first glance the PNP in the SCR is no longer gated with a BASE connection and it looks like it's just functioning as a diode.



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  • cgraceycgracey Posts: 11,946
    edited 2019-09-04 - 22:52:18
    Today we built up seven new P2 Eval boards with the new silicon.

    They all work, and one board has an expected 17mA VIO quiescent draw, as we previously measured a 192-ohm path to GND on V2427 on one of the glob-top chips. The other six boards have near-zero quiescent VIO current, which is normal.

    Meanwhile, ON Semi is checking everything. They suspect it is NOT a manufacturing problem, so they are doing an XOR check of old vs. new GDS data. That will reveal any difference immediately.

    It's strange that we have chips that work well.

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  • cgracey wrote: »
    Today we built up seven new P2 Eval boards with the new silicon.

    They all work, and one board has an expected 17mA VIO quiescent draw, as we previously measured a 192-ohm path to GND on V2427 on one of the glob-top chips. The other six boards have near-zero quiescent VIO current, which is normal.

    Meanwhile, ON Semi is checking everything. They suspect it is NOT a manufacturing problem, so they are doing an XOR check of old vs. new GDS data. That will reveal any difference immediately.

    It's strange that we have chips that work well.
    Nice! This are all glob top chips? Are there any restrictions as to how they are used?

  • cgraceycgracey Posts: 11,946
    edited 2019-09-04 - 22:58:30
    These are all glob tops. They are not as reliable as the Amkor packages, but they work.
  • jmgjmg Posts: 14,135
    cgracey wrote: »
    Today we built up seven new P2 Eval boards with the new silicon.

    They all work, and one board has an expected 17mA VIO quiescent draw, as we previously measured a 192-ohm path to GND on V2427 on one of the glob-top chips. The other six boards have near-zero quiescent VIO current, which is normal.
    Does that IO bank otherwise work ?
    You could measure the mV deviation from VIO on the output, to get an idea of the shared resistances, and that could verify which area is drawing the current.

    cgracey wrote: »
    Meanwhile, ON Semi is checking everything. They suspect it is NOT a manufacturing problem, so they are doing an XOR check of old vs. new GDS data. That will reveal any difference immediately.
    It's strange that we have chips that work well.
    I guess that's an easy compare to do, but does not quite fit the symptoms...?

  • cgracey wrote: »
    These are all glob tops. They are not as reliable as the Amkor packages, but they work.
    What are you going to do with these new boards? Maybe you should send one to ntosme2. He's making great progress on getting GCC working for P2.
  • AleAle Posts: 2,357
    I want a board, even an old one.
  • I feel like I have last year's smartphone but this year's improved model has a "folding screen" problem :wink: Both are good and both are not so good anymore :disappointed:
    But the new model will be good, once the wrinkles are ironed out that is :smile:

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