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P2 Unboxing - while waiting for Chip, we decided to open the box! — Parallax Forums

P2 Unboxing - while waiting for Chip, we decided to open the box!

Comments

  • cgraceycgracey Posts: 14,133
    On my way down there...
  • PublisonPublison Posts: 12,366
    Good times! :smile:
  • potatoheadpotatohead Posts: 10,254
    Exciting times! These are the ones that will just work!

    I can feel it. Hoping, hoping....

    Go Parallax! Onward to test and production.

    And then our P2 expo. I got my Rocklin trip all planned and ready to go.

    (Has been way too long guys)
  • David BetzDavid Betz Posts: 14,511
    Looking good so far! I hope they work!
  • Ken GraceyKen Gracey Posts: 7,386
    Chip says so far, so good. Some questions and answers show up as he works. One never knows the outcome this early, of course.

    Ken Gracey
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  • David BetzDavid Betz Posts: 14,511
    Very encouraging! Congratulations!
  • David BetzDavid Betz Posts: 14,511
    When can we place our orders for the new P2 boards? :smile:
  • jmgjmg Posts: 15,145
    cgracey wrote: »
    On my way down there...

    Should you send a couple of these to Peter, so he can mount on P2D2, and run parallel tests ?
  • cgraceycgracey Posts: 14,133
    We had a few bumpy starts, but the chip seems just fine. This glob top prototype packaging is pretty delicate. After our rework efforts with the original boards, we discovered that some internal bond wires were broken. Fortunately, they weren't on critical pins. We also had issues with the crystal suffering some ohmic contamination from the flux.
  • David BetzDavid Betz Posts: 14,511
    The chip is just fine? That’s great news!
  • jmgjmg Posts: 15,145
    cgracey wrote: »
    We had a few bumpy starts, but the chip seems just fine...

    What's the errata list looking like now ?
    Any mA/MHz and upper MHz indications yet ?

  • jmgjmg Posts: 15,145
    cgracey wrote: »
    .. This glob top prototype packaging is pretty delicate. After our rework efforts with the original boards, we discovered that some internal bond wires were broken. Fortunately, they weren't on critical pins. We also had issues with the crystal suffering some ohmic contamination from the flux.
    Hmm. Maybe that package needs low temperature solder and extreme care ?

  • Luis DigitalLuis Digital Posts: 371
    That is the real silicon?

    https://4shared.com/photo/zjSFZ4Utgm/P2_online.html :o
  • jmgjmg Posts: 15,145
    Luis Digital wrote: »
    That is the real silicon?

    https://4shared.com/photo/zjSFZ4Utgm/P2_online.html :o

    You mean the newest P2-ES2 samples ?
    Yes, first handful in a low volume glob-top package, the better packages are still being done, as the die are send to a packaging company for that step. Those will have better labels too :)
  • Luis DigitalLuis Digital Posts: 371
    jmg wrote: »
    Luis Digital wrote: »
    That is the real silicon?

    https://4shared.com/photo/zjSFZ4Utgm/P2_online.html :o

    You mean the newest P2-ES2 samples ?
    Yes, first handful in a low volume glob-top package, the better packages are still being done, as the die are send to a packaging company for that step. Those will have better labels too :)

    I meant about the big area on chip than I mark in red in the photo.
  • TubularTubular Posts: 4,622
    That's right Luis, that red dots are the approximate outline of the chip itself. I think its something like 10mmx 10mm, similar to the exposed ground pad underneath
  • jmgjmg Posts: 15,145
    Luis Digital wrote: »
    I meant about the big area on chip than I mark in red in the photo.

    Oh, you mean the actual P2 physical die size - yes, it is quite large, just a little smaller than the exposed PAD on the rear side. IIRC ~8.5mm/side was mentioned

  • cgraceycgracey Posts: 14,133
    I am driving home now. Once I get there, I will be able to do all kinds of tests for current consumption versus megahertz, etc. I might go to sleep tonight and get a start on that in the morning. Anyway, the chip looks just fine. No sign of any problems. This globtop packaging is not the greatest, though. I think the idea of using lower-temperature solder would be a good one.
  • potatoheadpotatohead Posts: 10,254
    Great news Chip! Drive safe
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    cgracey wrote:
    I might go to sleep tonight and get a start on that in the morning.
    Yeah, right, like you're gonna be able to sleep! Nonetheless, good luck with the testing! This is a huge day for you and for Parallax. :)

    -Phil
  • cgraceycgracey Posts: 14,133
    edited 2019-08-01 05:35
    Thanks, Guys! This is a product of everyone's efforts here.
  • jmgjmg Posts: 15,145
    This is the summary of what was fixed/changed in P2es2
    * All known prior bugs fixed. (this includes the verilog sign oops, that killed quadrature counting & other things)
    *Clock-gating implemented, reduces power by ~40%.
    *PLL filter modified to reduce jitter and improve lock.
    *System counter extended to 64 bits. GETCT WC retrieves upper 32-bits.
    *Streamer has many new modes with SINC1/SINC2 ADC conversions for Goertzel mode.
    *HDMI mode added to streamer with ascending and descending pinouts for easy PCB layout.
    *SINC2/SINC3 filters added to smart pins for improving ENOB in ADC conversions.
    *Each cog has four 8-bit sample-per-clock ADC channels that feed from new smart pin 'scope' modes.
    *BITL/BITH/BITC/BITNC/BITZ/BITNZ/BITRND/BITNOT can now work on a span of bits (+S[9:5] bits). Prior SETQ overrides S[9:5].
    *DIRx/OUTx/FLTx/DRVx can now work on a span of pins (+D[10:6] pins). Prior SETQ overrides D[10:6].
    *WRPIN/WXPIN/WYPIN/AKPIN can now work on a span of pins (+S[10:6] pins). Prior SETQ overrides S[10:6].
    *BIT_DAC output now has two 4-bit settings for low and high states, instead of one 8-bit high-state setting.
    *RDxxxx/WRxxxx+PTRx expressions now index -16..+16 with updating and -32..+31 without updating.
    *Sensible PTRx behavior implemented for 'SETQ(2) + RDLONG/WRLONG/WMLONG' operations.
    *RDLUT/WRLUT can now handle PTRx expressions.
    *Cog LUT sharing is now glitch-free.
    *POP now returns Z=1 if result=0, used to return result[30].
    *XORO32 improved.
    *Main PRNG upgraded to Xoroshiro128**.

    With that many changes, it would be nice to get these into more hands, to confirm existing code still works - eg
    * confirm USB Code is still OK
    * check PLL noise/lock effects are ideally better, but at least not worse
    * HDMI code is going to be very interesting, I think someone had that working, in a SW-assisted manner ?
  • evanhevanh Posts: 15,187
    I doubt the globtops are going anywhere.
  • roglohrogloh Posts: 5,167
    cgracey wrote: »
    Anyway, the chip looks just fine. No sign of any problems.
    Sounds like good news so far. A nice day's work.
  • RaymanRayman Posts: 13,889
    There was some bug with the color space converter too, right?
    Something that made NTSC not work, I think...
  • RaymanRayman Posts: 13,889
    of all the fixes in the list, HDMI is the thing I care most about...
  • samuellsamuell Posts: 554
    Hi Chip,

    These packages look different than the previous glob-top ones. Or maybe I'm not recalling correctly, but I had the notion that the previous ones were actual glob-tops with rounded edges and all.

    The bug fixes are promising, and enough reason for me to buy one first hand, once the finished chips are available.

    Kind regards, Samuel Lourenço
  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2019-08-02 04:36
    The original globtops look very similar. The P2s that were mounted on the eval boards weren't the globtops, they were the production package.
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  • samuellsamuell Posts: 554
    edited 2019-08-02 07:23
    Although I was aware that the chips soldered to the boards were provided on their "final" package, I was recalling incorrectly that the original glop-top samples looked different when compared to the new ones. After all, the new glop-top is not flat as well.

    Kind regards, Samuel Lourenço
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