Anyone tried P2 Smartpin SPI mode?

Peter JakackiPeter Jakacki Posts: 8,772
edited 2019-06-16 - 23:13:11 in Propeller 2
I know I could trawl through this forum and the documentation if I wanted to find out more about using Smart pins in SPI bus mode, but has anyone done so yet?

At present my bit-bashed SPI bus runs about 1/10 of the P2 clock so I can run my SD read routines up to 30MHz with about 3MB/s read speed.
Now SD card SPI frequency can be as high as 50MHz so what I would like to do is run as high as I can while keeping the P2 clock frequency low.

The smart pins should allow me to do this and admittedly I haven't really bothered to work out what I need to do yet but I thought I'd throw this question out there.

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Comments

  • No, I haven't tried as yet.

    Chip added something for adjusting the rx sampling point but I can't remember any details about the timing info or how it was achieved. The docs just say "X[5] = 0 selects the A input sample just before the B input edge was registered."

    I don't know if X[5] = 0 is the normal digital input mode. X[5] = 1 reads like it should be the normal digital input mode.

    As for tx, X[5] = 0 looks to be for when wanting to constantly enable/disable tx, like for 1-bit SPI. Otherwise I'd guess X[5] = 1 will be more straight forward to use.


    The big thing is SPI smartpins, both rx and tx, operate on an external clock (B input). This has implications for understanding how it all works. For tx in particular, the updated shift out appears at the physical pin 2-3 sysclocks after the external SPI clock has transitioned the clock edge. Which means there is heaps of time to use that same edge for slave device clock edge. It also limits max data rate. Probably safest to use 1/4 sysclock.

    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • evanh wrote: »
    As for tx, X[5] = 0 looks to be for when wanting to constantly enable/disable tx, like for 1-bit SPI. Otherwise I'd guess X[5] = 1 will be more straight forward to use.
    Err, not 1-bit SPI, that's too vague, make that X[5] = 0 is for 1-bit SD mode with bidirectional data pin. There is some other systems that do bidirectional serial too.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • Mark_TMark_T Posts: 1,981
    edited 2019-06-18 - 08:47:43
    Check out FredBlais's reply in my similar thread: https://forums.parallax.com/discussion/169846/smartpin-spi-bidirectional-sample-code (I haven't followed up on this yet)
  • I have been trying to get something on spi working anyone have any suggestions? With a clear basic explanation??
    Thanks
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  • More discoveries found in the smartpins topic - https://forums.parallax.com/discussion/comment/1474279/#Comment_1474279
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • samuellsamuell Posts: 492
    edited 2019-07-27 - 13:47:40
    I didn't, but surely I will need to do that in the future. I'm hoping that the C libraries will implement I2C and SPI, so I don't have to do bit banging (yuck).

    Kind regards, Samuel Lourenço
  • evanhevanh Posts: 8,259
    edited 2019-07-27 - 14:54:32
    Hehe, don't worry there Samuell. I hope to document things better.

    Bit-bashing ain't so bad, it's simple to code and understand and it can also reach to sysclock/8 so it's no slouch really. I hadn't looked into it previously because SPI seemed just fine bit-bashed all the way. Libraries will likely continue to using it simply because it doesn't require special initialisation.

    Although they may upgrade to smartpins + bit-bashed clock. This can handle send and receive at once without slowdown. And with the OUT-as-input-B trick this can even have tight tx to clock alignment. Hmm, good point, bit-bashed SPI clock should be able to do a very clean sysclock/4 then.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • evanh wrote: »
    Hehe, don't worry there Samuell. I hope to document things better.

    Bit-bashing ain't so bad, it's simple to code and understand and it can also reach to sysclock/8 so it's no slouch really. I hadn't looked into it previously because SPI seemed just fine bit-bashed all the way. Libraries will likely continue to using it simply because it doesn't require special initialisation.

    Although they may upgrade to smartpins + bit-bashed clock. This can handle send and receive at once without slowdown. And with the OUT-as-input-B trick this can even have tight tx to clock alignment. Hmm, good point, bit-bashed SPI clock should be able to do a very clean sysclock/4 then.
    Well, when I implement bit bashing, I end up with ugly code (I'm not a good coder in style, I admit). Also, controlling pins with C directly it is kind of slow. Already tried that with the P1, and it was far from 1MHz.

    Kind regards, Samuel Lourenço
  • I'm no C guy so not sure how much I can help but I've been working on SPI for the P2 (in the form of SD) so might be of some help. I've actually been planning on taking what I've learned and building out an SPI object. I've got a couple P2ASM examples in my SD thread. I guess I'd ask what SPI clock you are trying to hit and what your planned sysclock would be. If bit-bashing would work *sysclock /8 iirc you're looking for something like this.
    pri send(outv) | c, i       '   Send eight bits, then raise di.
    
            i := di
            c := clk
        asm
                rol     outv,       #24        
                rep     #.end_send, #8
                rol     outv,       #1      wc
                drvl    c
                drvc    i
                drvh    c 
    .end_send     
                drvh    i    
    endasm
    
    
    pri read : r  | c, o        '   Read eight bits from the card.
    
            c := clk
            o := do
        asm
            mov     r,          #0
            rep     #.end_read, #8
            drvl    c
            waitx   #15    '' !! 13 safe for up to 160 mhz, 14 for 320mhz, 57@320mhz external, 29@160mhz,15@80mhz
            testp   o               wc  
            drvh    c   
            rcl     r,          #1
    .end_read
        endasm
    

    That's not including init code. Setup is pretty easy and the full SD driver RC2 is posted in the first post. I'm still testing RC3 that uses smartpins but those look something like this (much more setup required though)
    pri send(outv) | c, i      '   Send eight bits, then raise di.
    
            i := di
            c := clk
            asm
                    SHL outv,           #32-8       ' Set MSB First
                    REV outv                        ' Set MSB First
                    wypin   outv,       i           ' data !!
                    rdpin   pa,         c
                    wypin   #byteclks,  c           'start clock, tx data    
            .busy   testp               c   wc
            if_nc   jmp     #.busy    
                    wypin   #$FF,       i
    endasm
         
    pri read   | c, o, t     '   Read eight bits from the card.
    
            c   := clk
            o   := do      
        asm    
                rdpin   pa,         c
                wypin   #byteclks,  c           ' start clock            
        .busy   testp   c                   wc
        if_nc   jmp     #.busy
                rdpin   t,          o           ' get data
                rev     t                           
                and     t,          #$ff                                  
        endasm
        return t    
    

    If you just need to send / receive 8 bits these could easily be used. Shouldn't be to hard to allow up to 32 bits. Again, all P2ASM with Fastspin.
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