#### Equip your Genius

Welcome to the Parallax Discussion Forums, sign-up to participate.

# Relationship between the P2 global clock and individual core clock

Posts: 535
edited April 2019
Hi,

What is the relationship between the global clock and core clock on the P2? I know that the core clock on the P1 would be 20MHz for a 80MHz frequency. Is the clock divided in the same way for the P2?

Also, what is the percentage of instructions that only need one clock cycle?

On another note, I've read that the clock will be reduced to 160MHz for the final version, due to thermal issues. Could someone confirm that?

Kind regards, Samuel Lourenço

## Comments

• Posts: 4,583
All the cores (COGs) share the same clock, both in P1 and P2. So the COGs in P1 are clocked at 80 MHz. I think you were confused by the fact that (most) P1 instructions take 4 clock cycles to complete, so they can execute 20 million instructions per second.

On P2 most instructions take 2 cycles to complete, so the peak throughput at 160 MHz is 80 million instructions per second. The Parallax Propeller 2 instructions spreadsheet (at https://docs.google.com/spreadsheets/d/1usUcCCQVp3liAqENX9rvX-XVqJomMREhKYExM_taG0A/edit?usp=sharing) gives the exact cycle count for all instructions. Generally math instructions are 2 cycles, branches are 4 cycles (much longer in hubexec) and hub access instructions are variable depending on hub window timing. There are exceptions to all of these general rules, so see the spreadsheet for details.
• Posts: 660
samuell wrote: »
On another note, I've read that the clock will be reduced to 160MHz for the final version, due to thermal issues. Could someone confirm that?

Kind regards, Samuel Lourenço

It's not because of thermal issues!
It has more to do with signal length (longer=slower) and the fixed maximum area of the silicon wafer (higher fanout = slower, lower fanout = more duplicated paths = more area).

When they say that they're shooting for 160 MHz, that means a guaranteed number over the entire operating temperature range span (ambient temperature extremely cold or super hot). If you run the chip with its surroundings at room temperature, you're going to be able to get it to go much faster than the rated spec.
• Posts: 1,091
They wouldn't have added the HDMI streamer mode if the chip couldn't hit 250MHz
(altough IIRC it may need some kind of heat sink or fan?)
• Posts: 14,571
samuell wrote: »
..

On another note, I've read that the clock will be reduced to 160MHz for the final version, due to thermal issues. Could someone confirm that?

I think these are the latest from Chip :
Wendy reminded me yesterday that timing closure for the new P2 is set from -55C to +150C junction temperature. Our package Tja is ~20C/W. The anticipated power dissipation was ~2.25W. This would result in a ~45C (20×2.25) rise in junction temperature over ambient temperature, which affords us a -55C to +85C packaged temperature range with ~20C (150-45-85) allowance for local hot spots on the die.

After the tapeout is complete, we will be able to generate a graph of temperature vs Fmax.
..
Wendy just told me that she was able to wrap up timing across all corners at 175MHz, after all.
..
2019-03-30 - 12:00:25 Flag
Wendy is running the simulations and she got me some data on current during download (one cog):

Current silicon = 77mA
Next silicon = 40mA

It's not as low as I'd hoped, but about half the current is not bad. The clock tree is actually taking half of that 40mA.

Wendy should have the high-power simulation results back soon. The chip is definitely going to run cooler than before.

So the 175MHz is PVT with a -55C to +150C junction temperature.
There should be some higher MHz possible, with tighter Vdd and some lowering of TJ max
The stretch goal is 250MHz, for HDMI, and I think that 175MHz is slightly ahead of the current P2es die, & they seems to manage a typical of 250MHz ok.
• Posts: 17,172
edited April 2019
The respin has reached 175MHz for the full range spec IIRC. We don’t have a speed for just a commercial range yet.

We are all hoping the respin will still achieve 300-350+MHz overclocking but we will have to wait for real silicon to test it.

There are a lot of powerful instructions that often reduce the number of instructions to achieve the same result.
• Posts: 535
Thanks to all! I've made a big confusion. It is more clear now.
jmg wrote: »
samuell wrote: »
..

On another note, I've read that the clock will be reduced to 160MHz for the final version, due to thermal issues. Could someone confirm that?

I think these are the latest from Chip :
Wendy reminded me yesterday that timing closure for the new P2 is set from -55C to +150C junction temperature. Our package Tja is ~20C/W. The anticipated power dissipation was ~2.25W. This would result in a ~45C (20×2.25) rise in junction temperature over ambient temperature, which affords us a -55C to +85C packaged temperature range with ~20C (150-45-85) allowance for local hot spots on the die.

After the tapeout is complete, we will be able to generate a graph of temperature vs Fmax.
..
Wendy just told me that she was able to wrap up timing across all corners at 175MHz, after all.
..
2019-03-30 - 12:00:25 Flag
Wendy is running the simulations and she got me some data on current during download (one cog):

Current silicon = 77mA
Next silicon = 40mA

It's not as low as I'd hoped, but about half the current is not bad. The clock tree is actually taking half of that 40mA.

Wendy should have the high-power simulation results back soon. The chip is definitely going to run cooler than before.

So the 175MHz is PVT with a -55C to +150C junction temperature.
There should be some higher MHz possible, with tighter Vdd and some lowering of TJ max
The stretch goal is 250MHz, for HDMI, and I think that 175MHz is slightly ahead of the current P2es die, & they seems to manage a typical of 250MHz ok.
So, the final P2 silicon is aiming for 250MHz stable?

Kind regards, Samuel Lourenço
Sign In or Register to comment.