About the upcoming P2

Hi,

This is a set of questions to Ken and also Chip. I would like to write an article the upcoming P2 in my blog, and also make a review of the P2 evaluation board (just a brief one, without delving into details, since it is just an evaluation board and not the final product). Someone told me that it might pose a problem if i do a review. So I would like to be directed by Ken about what I can talk about, and what I can't mention.

Also, I would like to ask the following questions:
- What is the expected release date/month/range?
- What will be the flavors (I read that it will be four, ranging from two cogs to the full P2)?
- Details about the flavors?

Kind regards, Samuel Lourenço

Comments

  • jmgjmg Posts: 13,613
    samuell wrote: »
    Also, I would like to ask the following questions:
    - What is the expected release date/month/range?
    - What will be the flavors (I read that it will be four, ranging from two cogs to the full P2)?
    - Details about the flavors?
    In other posts, Chip has mentioned OnSemi are deep into place and route of the final P2 verilog. No MHZ indicators yet.
    ROM appears to be 'final/release candidate' form, but not fully tested yet, but it is a late merge item in the OnSemi flow.
    Flavors will be what OnSemi makes, and right now all they are making, is the 8 COG 512k P2. Anything else is over-the-horizon road map ..


  • Hi jmg,

    The issue is that the information is too scattered. I thought that the clock speed was set to 180MHz, although the prototype P2 is certainly highly overclockable, which may suggest that it could be higher.

    Anyway, I really need some pointers here, form both Chip and Ken, even if the article ends up being about my first impressions on the P2 Eval.

    Kind regards, Samuel Lourenço
  • Flavors will almost certainly be determined by marketing considerations. As JMG says right now we are getting 8 cog + 512K RAM, which about maxes out the die at this process 160 nm target resolution. Future revisions could go for smaller dies via less cogs or RAM, or higher run speeds via smaller target resolutions. As far as we know Parallax have done nothing but blue-sky those possibilities at this point. They have to get something marketable out the door so they can start recovering their investment in the whole project.

    Right now there are about 150 packaged flawed prototype evaluation P2's in about 100 ES boards, about half that many P2D2's, and a few blobs, and those of us who snagged one are just exercising them to see if there are any more flaws before the final first-gen production silicon is spun. Personally I am closely watching the PLL thread; that's something that will affect all of us and any future flavors.
  • jmgjmg Posts: 13,613
    samuell wrote: »
    ... I thought that the clock speed was set to 180MHz, although the prototype P2 is certainly highly overclockable, which may suggest that it could be higher.
    Yes, 180MHz was the original design target spec point. As you say, it can run well above that, and I think the 250MHz HDMI point has made that a new MHz of interest.
    Given MHz is somewhat elastic combination of Voltage and Temperature, they may do a lower temperature Max, and tighter Vdd, to hit the 250MHz point.
    200MHz is another spec point of psychological interest.
    Other vendors have Industrial and Consumer spec devices, that are the same die.

    Chip did add significant logic, so the final MHz OnSemi can hit, will be interesting to see.

    samuell wrote: »
    ... even if the article ends up being about my first impressions on the P2 Eval.
    Sounds a good idea.
    Right now, all that exists are the Engineering samples so that is all you can write about, but that's still a lot to digest and is a very good indicator of what the final P2+ will be.
  • I'm sure Ken will make announcements when the time's right.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • Ken GraceyKen Gracey Posts: 6,420
    edited 2019-02-16 - 23:52:10
    samuell wrote: »
    Hi,

    This is a set of questions to Ken and also Chip. I would like to write an article the upcoming P2 in my blog, and also make a review of the P2 evaluation board (just a brief one, without delving into details, since it is just an evaluation board and not the final product). Someone told me that it might pose a problem if i do a review. So I would like to be directed by Ken about what I can talk about, and what I can't mention.

    Also, I would like to ask the following questions:
    - What is the expected release date/month/range?
    - What will be the flavors (I read that it will be four, ranging from two cogs to the full P2)?
    - Details about the flavors?

    Kind regards, Samuel Lourenço

    Hey Samuel,

    It's really easy to get misinformed about what's really going on when reading old forum threads. We're working to build a web site (with the people on this forum) to provide a consolidated location for our roadmap, datasheets, links to tools, etc. Such an information repository would save us a lot of time right now. We intend to be entirely, totally transparent about the whole effort. There's really nothing to hide anyway. We haven't got the skills or budget for big-company marketing hype either, so WYSIWYG.

    You can write whatever you wish. Just keep in mind exactly *where we are* in the pipeline. Some people come here expecting a complete Spin 2, pricing, and applications - ready to go. We're in the final stages of development and the people with P2 Evaluation Boards are contributing and testing with us and for us. Somebody looking for a ready-to-go multicore chip for their CNC machine could be disappointed (and maybe not, depending on what's happening right now). You already understand this, I'm sure.

    To your questions. The best I can see at this stage is:

    Release. We will have another 10 units to 1K units (still talking about this), packaged and tested in our Rocklin office in June. We just signed an Engineering Change Order and paid a substantial invoice for additional services - turning more Verilog into synthesized design. This added time (the time for Chip to write the code and test, and now time for synthesis and characterization) and expense. The ON schedule is very clear and they manage [us] very well, according to a schedule.

    Production chips follow after we verify these, and they take 12 weeks. This means that if we ordered on July 1st we'd have production quantities on October 1st. These lead times are really painful at this stage! Help Chip get this thing finalized.

    Flavors This is something we've talked about with ON. The discussion has been oriented on smaller varieties, mostly. Guess you could say we have the roadmap out of order here. Maybe look at the P2 as the patriarch and now it needs some children to be a family. No decisions have been made, but it's clear that small switches in the Verilog code could enable smaller die size and features easily.

    Hope this helps.

    Ken Gracey
  • Thanks Ken and jmg. I'll make sure that it is clear that the sample is just an engineering one and that the P2 wasn't released yet.

    As for the release date, I understand the pain. There are many people waiting for this chip, but that's how things run. My longest project took one year to be released, between experiments, failed designs and corrections, and that was just a PCB layout. For such a complex chip as yours, and considering the roadblocks this project encountered, it is very understandable why is it taking that time. Anyway, I rather prefer to wait and have a fine tuned chip in my hands later.

    Kind regards, Samuel Lourenço
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