PLL fix possibly found

cgraceycgracey Posts: 10,863
edited 2019-02-09 - 07:45:48 in Propeller 2
It's known that as the 6-bit crystal divisor increases, jitter becomes worse.

There are two programmable resistors in the PLL bias voltage feedback circuit that are controlled by the same 6-bit value used for dividing the crystal frequency.

As the crystal divisor increases, the bias feedback becomes weaker. This seemed to be the optimal recipe during design simulations of the PLL. We have jitter problems, though, that increase with the crystal divisor value, which is also the programmable resistor value.

I did an experiment tonight using the P2-Eval board, where I effectively decoupled the relationship between the crystal frequency division and the feedback strength.

What I did was use a function generator to drive a low frequency square wave into XI, via the plated XI hole on the PCB, to simulate a highly-divided crystal frequency, while keeping the 6-bit crystal divisor value at %000000 for maximum feedback strength.

I can drive very low frequencies, like 100KHz, into XI, with the crystal divisor set to %000000 for maximum feedback strength, and use the 10-bit VCO divider to wind up the VCO to 1024 times 100KHz, to get 102.4MHz with no visible jitter on a 640x480 VGA display. This means the PFD is only updating at 100KHz, as it generates a clean 102.4MHz using maximum feedback strength. So, it looks like our problem has mainly been weak feedback, not necessarily a low feedback rate (PFD frequency).

Could you guys please do some checking on your boards to confirm this?

If this solves the problem, it just means we need to zero out the settings in the custom layout to the programmable resistors, so that they are always low-impedance. This would be very simple to do.

Comments

  • Did you remove the crystal?

    Is %CC=00 XINPUT? Documents say XI is "ignored." It seems to work.

    This photo is a 1 second exposure. The 102.4Mhz is divided by 8 for the scope. 15nS p-p jitter? That's less than 1 pixel at VGA.

    Does the PFD drive change between XDIV=2 and XDIV=3? That would match the large increase in spurs I saw.

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  • I did not remove the crystal. I just kind of over drove it. I didn't even bother to change the crystal setting.
  • cgraceycgracey Posts: 10,863
    edited 2019-02-10 - 01:09:21
    Saucy, can you please see what the jitter is with a 200KHz input and a 500KHz input?
  • It's important to keep the crystal divider at %000000 to cause the strongest feedback
  • jmgjmg Posts: 13,092
    This photo is a 1 second exposure. The 102.4Mhz is divided by 8 for the scope. 15nS p-p jitter? That's less than 1 pixel at VGA.

    The best capture would be VGA pixel rate, which I think here is 25.6MHz or /4 ?

    Another test point would be to swap in a 5MHz Xtal, and test PLLs that were using Xtal/4, to instead use the Xtal/1 higher feedback setting ?
  • jmgjmg Posts: 13,092
    cgracey wrote: »
    What I did was use a function generator to drive a low frequency square wave into XI, via the plated XI hole on the PCB, to simulate a highly-divided crystal frequency, while keeping the 6-bit crystal divisor value at %000000 for maximum feedback strength.
    hmm...
    Not sure this is a lot better ? - I found a FOX924B 20.000MHz TCXO - a 2.5ppm CMOS part (so we have exactly the same MHz)
    and fed that into a HC4060 binary divider, then corrected P2 settings to give 20MHz on a pin, and HC4046 Phase compared against the FOX924

    First one is 6-bit crystal divisor value at %000000, XI = 20M/64
    Second one is XI=20M/16
    3rd one is that zoomed, shoes ~ 50kHz ringing, but somewhat lazy in nature. Strange.
    4th plot is spectrum, you can see the 1.25MHz PFD there, but that 50KHz ringing is quite dominant The ~1.3MHz on blue trace, is checking the smps noise points
  • jmgjmg Posts: 13,092
    edited 2019-02-10 - 09:54:48
    and just to compare apples-apples, because the filter did change, here is this old lowest PFD with gain change
    '%1_111111_0111111111_1111_10_00 HUBSET 200,000 WAITX %1_111111_0111111111_1111_10_11 HUBSET',$0D

    I've pasted the same-scale MAX gain image, from above, into the same plot, (both at 312500Hz PFD, but Gain differs ) so they are certainly different in behaviour, mostly being the disturbance frequency.

    Ripple peaks on spectrum at about 4.5kHz vs 50kHz for highest gain, so the gain certainly moves something.
  • cgraceycgracey Posts: 10,863
    edited 2019-02-10 - 11:16:53
    Thanks for doing all those tests, Jmg.

    I've been running SPICE simulations and it's looking like it is a good thing to have the R-C-R-C loop filter set up so that the first R is fixed and lower-impedance, while the second R remains variable, as it currently is. This way, it settles quickly and doesn't ring much. There's no way to test this on the current silicon, though, since both resistors are controlled by the 6-bit crystal divider.

    Here is what the BIASp looks like with a 200KHz input being multiplied 1000x to get 200MHz:

    PLL_200KHz_to_200MHz_BIASp.png
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  • I think we can live with it the way it is...
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  • cgraceycgracey Posts: 10,863
    edited 2019-02-12 - 20:54:13
    Here is BIASp with a 25MHz input being multiplied to 200MHz:

    PLL_25MHz_to_200MHz_BIASp.png
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  • jmgjmg Posts: 13,092
    cgracey wrote: »
    Here is what the BIASp looks like with a 200KHz input being multiplied 1000x to get 200MHz:

    Given the 4046 saturates at the rails, and so flattens somewhat away from the mid-point, I'd rate the internal /64 as having a larger deviation

    Can you try spice runs with 312500Hz PFD, with zero XDIV (XI = 312500Hz) and then with XI = 20MHz needing XDIV 64 ? In my tests I had VCO at 180MHz.

    - and add some disturbance to the PLL, to see how it manages following of variations - perhaps a small step-toggle of natural frequency every 500us ?

    It would be nice to see the same dominant single frequency noise come from Spice, as from the test bench.

    It's still unclear why this does not lock more 'firmly', but the higher gain certainly moves the natural frequency here from just under 5kHz to appx 50kHz

    Below is a plot I found on google, showing VCO spectrum and the effect the closed loop has on noise.
    Inside the loop bandwidth, the noise is pushed down by the feedback action, but outside the bandwidth, the feedback cannot help, and actually makes things slightly worse.
    To me that means a higher bandwidth will push out that suppression area more, which has to lower the noise.
    This plot also shows there will be expected a dominant frequency in the noise, with a peak in the ballpark of the loop bandwidth.
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  • jmgjmg Posts: 13,092
    Here is the spectrum compare, so you can see the noise peak move with improved bandwidth. - same PFD, same VCO
    ie better bandwidth is good, provided that is stable with impulse.
    The curious peak at 87.5kHz seems to be a scope sampling artifact, as it moves when I change FFT bandwidth, but the other soft peaks stay as expected.
  • jmgjmg Posts: 13,092
    Rayman wrote: »
    I think we can live with it the way it is...

    Another approach would be to shift the GAIN bits to the 3 spare bits in the Clock Set fields, so GAIN can vary separate from XDIV.

    Given higher PFD is proven better, another mitigation would be to select higher MHz xtals.
    It seems 48/50MHz is a 'readily available' upper Xtal limit.
    TCXO/VCTCXO's are more common at 19.2MHz & 26MHz in best price points.
    ( TG-5035CJ-13N 19.2000M3 is stocked at Digikey & I see they have NT1612AA-48MHZ-END5173A, 864 stock, $1.19/1 )

    eg These ABM8W Xtals look to be well documented, and come in low CL versions that might match CC = %01 PCB/Pin capacitance :
    https://abracon.com/Resonators/ABM8W.pdf

  • Where might the 18-25k spur be coming from? It seems to be pretty stable, I haven't noticed temperature dependence yet. It's hard to heat up the board.
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    Invention is the Science of Laziness
  • For heating up I use an old style 500w halogen worklight, perhaps 2ft away

    I found a hair dryer didn't work, because the extra airflow helped to cool the surface of the board such that there was not much net heat gain
  • With the heat spreading capabilities of the P2ES EVAL board, a hair dryer blowing on the bottom very much sucks up the heat. The Propeller gets plenty hot.
    "There's no huge amount of massive material
    hidden in the rings that we can't see,
    the rings are almost pure ice."
  • jmgjmg Posts: 13,092
    Where might the 18-25k spur be coming from? It seems to be pretty stable, I haven't noticed temperature dependence yet. It's hard to heat up the board.

    That varies with the gain (DIVX) so it must be an artifact of the PLL filtering + VCO noise. It does not quite look like normal impulse settling, but it is not continually oscillating either.
    Your plot #1 and plot #3 show that a higher PFD gives reduced amplitude deviations.
    If the Xtal Osc works ok up to ~50MHz, that gives another means to increase PFD.
  • jmgjmg Posts: 13,092
    It seems to be pretty stable, I haven't noticed temperature dependence yet. It's hard to heat up the board.
    Nice plots, did you ever do the same for the P1 ?
    I wonder if there is anything to learn from the P1 PLL, tho it will have a PFD-XI in all cases.
    Look like 64MHz is lowest VCO spec in P1, with 4MHz Xtal, so that could compare against a P2 with XI=4MHz, fVCO = 256MHz or 128MHz or 192MHz ?, fSys = 64MHz
  • The close spur might be vco noise. Plot 4 does look like that for PLL on. I'm monitoring VCO/10.

    div=1, pfd=500k, mlt=400 jitter ~5nS p-p. That's a good improvement.
    div=40, pfd=500k, mlt=400 jitter ~10nS p-p or worse. What's interesting, this setting reduces the amplitude of the reference spurs at the cost of a bunch of others.

    I'm using a quickstart board as my clock divider. I keep the P1 pll off so it's not a source of phase noise.

    It looks like the P2 does not have XINPUT mode. That's a disappointment. For my earlier comments I may have been changing a commented out second set of hubset commands.


    Plot 6 is a frighteningly bad result with div=4, mlt=1000, pfd=125khz. It is far worse than my earlier tests with ~100k pfd frequency. Plot 7 is the same settings but at a different termprature. The spurs come and go as I touch or blow on the chip. Also strange is why the spurs at 500k are unchanged, shouldn't they be at 125k because we are dividing the input by 4? It might be the clock input or oscillator bleeding through to the VCO.

    Chip, the problem with your SPICE plots is that the voltages involved are very small. I was seeing 150khz pk-pk deviation at the /10 output I was monitoring. That's 1.5MHz deviation at the VCO. I'll estimate the VCO sensitivity at 200MHz/volt. So there might be 7.5mV of ripple at the VCO input. The graphs show about 333 pixels/volt. So that extreme deviation is 2.5 pixels. Typical VCO deviation is 200khz pk-pk on the other plots. About 1/3 of a pixel.
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    Invention is the Science of Laziness
  • jmg wrote: »
    Here is the spectrum compare, so you can see the noise peak move with improved bandwidth. - same PFD, same VCO
    ie better bandwidth is good, provided that is stable with impulse.
    The curious peak at 87.5kHz seems to be a scope sampling artifact, as it moves when I change FFT bandwidth, but the other soft peaks stay as expected.

    I'm seeing a spur at the input frequency in my tests. Note: 400k-312.5k = 87.5k The 87.5k peak is likely a real part of the signal, aliased from 312.5k.
    James https://github.com/SaucySoliton/

    Invention is the Science of Laziness
  • jmg wrote: »
    It seems to be pretty stable, I haven't noticed temperature dependence yet. It's hard to heat up the board.
    Nice plots, did you ever do the same for the P1 ?
    I wonder if there is anything to learn from the P1 PLL, tho it will have a PFD-XI in all cases.
    Look like 64MHz is lowest VCO spec in P1, with 4MHz Xtal, so that could compare against a P2 with XI=4MHz, fVCO = 256MHz or 128MHz or 192MHz ?, fSys = 64MHz

    It was easy enough to run the P1 on the same setup.

    P2 pfd 20M, noise peak 200k ratio 100
    P2 pfd 500k, noise peak 32k ratio 15.6
    P2 pfd 312k, noise peak 26k ratio 12
    P2 pfd 100k, noise peak 18k ratio 5.5

    P1 pfd 5M, noise peak 300k ratio 16.7

    Older tests: forums.parallax.com/discussion/comment/1429445/#Comment_1429445
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    Invention is the Science of Laziness
  • jmgjmg Posts: 13,092
    Plot 6 is a frighteningly bad result with div=4, mlt=1000, pfd=125khz. It is far worse than my earlier tests with ~100k pfd frequency. Plot 7 is the same settings but at a different termprature. The spurs come and go as I touch or blow on the chip. Also strange is why the spurs at 500k are unchanged, shouldn't they be at 125k because we are dividing the input by 4? It might be the clock input or oscillator bleeding through to the VCO.

    That quanta effect is rare, but I have captured it once (PFD would be 20M/16), and it was a 'transition zone' type behaviour, so did settle to no jumps as the part warmed, see below
    In my case, it seemed to have 2 preferred frequencies and was jumping between them, your plot 6 seems to have multiple jump points....

    These rare but erratic points are a real worry, as there is no predicting when or where the P2 will hit one of these 'hot spots'.
  • jmgjmg Posts: 13,092
    It was easy enough to run the P1 on the same setup.
    Is the one labeled P1-Xtal1, the Xtal direct and no PLL ?
    That should have very low jitter and be useful to checking noise floors in measuring systems ?

    P1 does not seem to have the lower frequency peaking effects that P2 displays ?
    P1 jitter of ~ 500Hz in 2.5MHz is about 1 part in 5000, which may be OK for P1 applications ?
  • jmgjmg Posts: 13,092
    It looks like the P2 does not have XINPUT mode. That's a disappointment. For my earlier comments I may have been changing a commented out second set of hubset commands.
    What do you want here ? - If you need external clock in, you select 0pF xtal case, and can DC or AC couple source to XI.
    Plot 6 is a frighteningly bad result with div=4, mlt=1000, pfd=125khz. It is far worse than my earlier tests with ~100k pfd frequency. Plot 7 is the same settings but at a different termprature. The spurs come and go as I touch or blow on the chip. Also strange is why the spurs at 500k are unchanged, shouldn't they be at 125k because we are dividing the input by 4? It might be the clock input or oscillator bleeding through to the VCO.
    Yes, I think that is clock input pickup, could be external or internal to P2. I've not seen layouts showing how close VCO is the the Clock buffers ?

    Focusing on that Plot 6, it seem to have a natural frequency of about 88us and about 11 steps within that.

    Chip's simulation above, labeled "Here is what the BIASp looks like with a 200KHz input being multiplied 1000x to get 200MHz:"
    has two zones, a coarse lock with triangle analog, and a finer lock with sawtooth analog.
    Most of the P2 captures show only coarse lock region.
    In this case the flat steps on that 90us sine modulation, suggest it has made it over the hump, and into the fine lock, but it is not stable there. On average, it is holding lock, but that has an 11 sample periodic wobble, quite sine nature.

    I've been reading up on injection locking, and that's a tricky technique where a PLL/VCO deliberately injects some channel-spacing impulse into the VCO, to snap-lock the VCO.
    It clearly needs care, as you want to snap, but still allow the next channel step. The plus side is you lower the average jitter, and get a little spread spectrum too, but it seems limited to known-channel-step designs.

    Running some numbers on that 88us beat frequency :

    Ideal Locked Period 1/12.5M = 8.0e-8
    Beat F seems to have close to 11 samples per cycle, which gives 11/125k = 88us

    1/(12.5M-1/88u) = 8.0072793448589626934e-8
    ans/10 = 8.0072793448589626934e-9 VCO period, 1/ans = 1.2488636363636363636e8 VCO Hz
    ans/125k = 999.0909 - is that close enough to possible injection lock point 999 ?

    Another clue is in the amplitude of that beat modulation sweep, looks to be very close to + 125kHz/2 to -125KHz/2 for a sweep range of 125k (=one PFD harmonic step)

    That could explain many things...
  • I found a case where the reduced feedback helps. With the PFD at 20MHz, there might be too much feedback with div=1. If I use div=4 with the same PFD freq, the noise peak goes down 5dB.
    div   pfd   carrier  noise SFDR
     1     80    47.8    -23    70.8 
     4     20    47.7    -15    62.7
     1     20    47.7    -10    57.7
    

    Of course, running the PFD at 80MHz is better.




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    Invention is the Science of Laziness
  • jmgjmg Posts: 13,092
    I found a case where the reduced feedback helps. With the PFD at 20MHz, there might be too much feedback with div=1. If I use div=4 with the same PFD freq, the noise peak goes down 5dB.
    ..
    Of course, running the PFD at 80MHz is better.
    Is that 80MHz running PLL still or direct Xtal drive ? It would be useful to get a noise-floor plot on the top trace, from an External Xtal Oscillator of 80MHz, No VCO/PLL ?
    I found a case where the reduced feedback helps. With the PFD at 20MHz, there might be too much feedback with div=1. If I use div=4 with the same PFD freq, the noise peak goes down 5dB.

    Interesting - maybe that strengthens the case to move the gain setting to spare 3 bits, independent of the Divider ?
    Not sure what that means in layout terms ?

  • cgraceycgracey Posts: 10,863
    edited 2019-02-13 - 01:42:46
    jmg wrote: »
    I found a case where the reduced feedback helps. With the PFD at 20MHz, there might be too much feedback with div=1. If I use div=4 with the same PFD freq, the noise peak goes down 5dB.
    ..
    Of course, running the PFD at 80MHz is better.
    Is that 80MHz running PLL still or direct Xtal drive ? It would be useful to get a noise-floor plot on the top trace, from an External Xtal Oscillator of 80MHz, No VCO/PLL ?
    I found a case where the reduced feedback helps. With the PFD at 20MHz, there might be too much feedback with div=1. If I use div=4 with the same PFD freq, the noise peak goes down 5dB.

    Interesting - maybe that strengthens the case to move the gain setting to spare 3 bits, independent of the Divider ?
    Not sure what that means in layout terms ?

    Jmg, sorry I have not gotten you more data today. Lots of interruptions. Anyway, we cannot generate any more control bits. We can only make changes to the pad, at this point, without adding new signals.

    I found that leaving the drive at the highest current setting, while allowing the loop filter resistor to change with the crystal divider is the best recipe for improvement.

    I don't understand, yet, why you and Saucy are seeing frequency artifacts that are not related to the PLL frequency.
  • jmgjmg Posts: 13,092
    edited 2019-02-13 - 02:01:04
    cgracey wrote: »
    .... Anyway, we cannot generate any more control bits. We can only make changes to the pad, at this point, without adding new signals.

    I found that leaving the drive at the highest current setting, while allowing the loop filter resistor to change with the crystal divider is the best recipe for improvement.
    OK, just have to pick the best compromise then..


    cgracey wrote: »
    I don't understand, yet, why you and Saucy are seeing frequency artifacts that are not related to the PLL frequency.

    I'm not sure they are totally unrelated, and can be explained by injection locking problems.
    The filter is going to naturally be sub-harmonic

    ... eg taking my example with less pure-sine, but still a dominant ~ 26KHz on the spectrum
    312.5k/26k = 12.0192 ie very close to 12 samples per fullcycle ( similar to the ~11-snap seen above in http://forums.parallax.com/uploads/thumbnails/FileUpload/aa/d3c7db0feb29c867b3a044b7fdb9ab.png)
    312.5k/12 = 26.042kHz

    Possible candidates : Square waves are odd harmonics, so they will have 511 and 513 snap points, but not 512
    (312.5k*(512+2/3)-160M)/8 = 26041 2 of 3 are *513, 1 of 3 is *512
    (312.5k*(512-2/3)-160M)/8 = -26041 2 of 3 are *511, 1 of 3 is *512
    and a possible proposed-fit snap-stream, than has a base-repeat of 12 samples, but averages 512 for a lock

    (512+513+513+512+513+512+512+511+511+512+511+512)/12 = 512.000
    ie that pattern of injection locking, will give a 26.042kHz beat 'sine', and an average that is perfectly locked.
    Note a ring-VCO does not have to lock on whole-numbers, as there are multiple edges in play, in all the stages, that can injection lock.
  • jmg wrote: »
    Is that 80MHz running PLL still or direct Xtal drive ? It would be useful to get a noise-floor plot on the top trace, from an External Xtal Oscillator of 80MHz, No VCO/PLL ?

    Plot 1 is XTAL2 with the on board crystal, 20MHz input, 20MHz PFD
    Plots 2,3 are with 80MHz external oscillator connected, Varied PFD
    Plot 4 is direct drive from 80MHz external oscillator.


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    Invention is the Science of Laziness
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