PLL wobble testing using HD VGA

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  • jmgjmg Posts: 13,618
    edited 2019-01-19 - 03:01:08
    ..and here is /64 to VCO=SysCLK=160MHz, with the higher 4046 filter bandwidth (5k6/22pF/5k6/15pF), the Phase noise here is significant, and not really random. Looks to favour 5~7kHz.
    Divide by 64 is at the extreme range end, with a PFD of a low 312.5kHz
  • jmgjmg Posts: 13,618
    edited 2019-01-19 - 04:15:16
    and this is the spectrum plot, to 200kHz with markers, of that ~ 33kHz ringing effect
    There is a broad peak at ~33.5 and another smaller one at ~67kHz, but nothing special shows at ~500kHz ?
    This close-in noise seems to follow the broad peak pattern of the lower divider values, that shows in the other plots.

    The second plot, adds a probe on 1V8, and there are peaks there at 320kHz and 345kHz, and another at 645kHz
  • jmgjmg Posts: 13,618
    cgracey wrote: »
    Jmg, I think this is great news!

    This means that the second-order RC filter on the VCO bias needs more resistance on the second resistor. I was suspecting something like this was happening. Simulations should confirm this.

    I'm not sure you can read too much into the captures, re magic filter values, as those skirts are broad, and the effect of the PLL feedback is to suppress the noise 'close in', whilst the noise further out cannot be corrected by the feedback.

    From the captures above :
    /1 pulls down VCO noise out to ~180kHz
    /2 pulls down VCO noise out to ~110kHz
    /4 pulls down VCO noise out to ~ 35kHz (on my 4046 test setup)

    Below is what google found for locked and not locked VCO noise, showing where the feedback helps (and where it does not)

    I was hoping to see the ~500KHz spurs, but even tho ~500k is now just -2dB on the revised filter, it is not appearing.
    780 x 413 - 31K
  • I connected some wideband AM and FM demodulators in Gnuradio. Noise from the power supply should appear as AM. Jitter should appear as FM.




    Plot 1 XDIV=64, spurs did not appear to be temperature dependent from this view
    Plot 2 XDIV=4
    Plot 3 XDIV=1
    all VCO=sysclock=160MHz
    Clock output pin on LDO. I did A/B testing with 33 ohms on the 3.3 line and did not notice any difference in any test.
    1579 x 2140 - 255K
    1579 x 2140 - 255K
    1579 x 2140 - 251K
    James https://github.com/SaucySoliton/

    Invention is the Science of Laziness
  • jmgjmg Posts: 13,618
    I connected some wideband AM and FM demodulators in Gnuradio. Noise from the power supply should appear as AM. Jitter should appear as FM.

    Plot 1 XDIV=64, spurs did not appear to be temperature dependent from this view
    Plot 2 XDIV=4
    Plot 3 XDIV=1
    all VCO=sysclock=160MHz
    Clock output pin on LDO. I did A/B testing with 33 ohms on the 3.3 line and did not notice any difference in any test.

    Hmm, on my /4, I get very similar spectrum below 200kHz, but I just cannot see any ~500kHz.
    I wonder if that varies from P2 to P2 ?

  • Is it switchmode reg vs LDO?
  • jmgjmg Posts: 13,618
    Tubular wrote: »
    Is it switchmode reg vs LDO?

    Good question, I run my tests at LDO setting, but flipping the jumpers to SMPS makes no discernible change to ~500kHz region.
    I can see SMPS birdies on my other probe on Vcc, main one at 312.5kHz, and others at 215kHz, 345 & 662kHz

    SaucySoliton plots have ~500kHz as the same amplitude, or greater, than the 30kHz close-in noise skirts, and the top FM trace has clear 500kHz present.
    With my 4046 phase detector filter -2dB at 500KHz, I expected to be able to see something quite similar.

    Unused LDOs warble away at 450~500KHz, (due to missing CL) but they are not connected, and quiet when they are connected.
  • Here's what I see on the XO xtal pin, around 80MHz (more detail visible than at 20MHz),
    zooming in from 1MHz span to a few kHz for detail on the left hand -8kHz and -7kHz spurs

    SSA_190120083127.png
    SSA_190120083256.png
    SSA_190120083341.png
    SSA_190120083455.png
    There's a bit of a party going on with spurs, basically.
  • VonSzarvasVonSzarvas Posts: 1,543
    edited 2019-01-20 - 13:57:45
    All this is being tested whilst the 1V8 is supplied from the on-board switcher, right ?

    Has anyone tried removing the VDD-1V8 header and injecting an external power supply instead of using the on-board switcher? Ideally an LDO-type of external source....


    Edit: Or an external switching source running at a different frequency. The EVAL switcher is set ~1470 kHz, which almost divides to JMG's birdies
  • Out the box settings, link from V1.8 to Vdd present.
  • Has anyone tried to run it form battery's to see if there is a difference?
  • Signal chain basics: Understand spurioussignals in high-speed ADCs :

    file:///D:/Downloads/EEOL_2011DEC19_AMP_TA_01.pdf




    https://www.analog.com/en/analog-dialogue/articles/analyzing-and-solving-fixed-frequency-spur-issues-in-high-precision-adc-signal-chains.html

    This article will cover five different application cases of specific design solutions for reducing spurs:

    Spur issues caused by dc-to-dc power supply radiation from the controller board.

    Spur issues caused by ac-to-dc adaptor noise through the external reference.

    Spur issues caused by analog input cable.

    Spur issues caused by interference coupled on the analog input cable.

    Spur issues caused by room lighting.

    Analyzing and Solving Fixed Frequency Spur Issues in High Precision ADC Signal Chains:

    Spur Issues Caused by AC-to-DC Adaptor Noise Coupling Through the External Reference
    ADCs quantize an analog signal into a digital code as referred to the ADCs’ dc reference voltage level. Therefore, the noise on the dc reference input will directly feed into the ADC’s output digital codes.
  • Looking at the 5V and VIO rails, both have the 7kHz spur popup when the P2 fires up on xtal oscillator. Doesn't
    seem to respond to adding bulk decoupling. Be good to look at the supply current, but I don't have a current probe.
  • jmgjmg Posts: 13,618
    Mark_T wrote: »
    Looking at the 5V and VIO rails, both have the 7kHz spur popup when the P2 fires up on xtal oscillator. Doesn't
    seem to respond to adding bulk decoupling. Be good to look at the supply current, but I don't have a current probe.

    Does that mean Xtal Osc + VCO/PLL, or the Xtal osc alone ? You can run just the Xtal, and I'd expect that to have no spuirs ?

  • jmgjmg Posts: 13,618
    VonSzarvas wrote: »
    Edit: Or an external switching source running at a different frequency. The EVAL switcher is set ~1470 kHz, which almost divides to JMG's birdies

    I can see a dominant 1488kHz if I probe the SMPS, but that does not appear significant on the Phase compare spectrum at all.
  • jmgjmg Posts: 13,618
    Mark_T wrote: »
    Here's what I see on the XO xtal pin, around 80MHz (more detail visible than at 20MHz),
    zooming in from 1MHz span to a few kHz for detail on the left hand -8kHz and -7kHz spurs
    Is that XO with no VCO or PLL enabled ? Are those 7~8~9kHz spurs stable, or do they move about with temperature ??
    What is your probe noise floor - ie touch the probe on the gnd connection point. (In my system there is a lot of residual noise about, scope itself, monitors etc)

  • VCO/PLL is on, as via:
    CON
    OSCMODE = $010c3f04
    FREQ = 160_000_000
    PUB demo | i
    clkset (OSCMODE, FREQ)


    The 7kHz peaks are unstable and seem to show wide phase noise spreading.
    Suggests something like motor-boating in the clock generation circuitry perhaps?
    They are a bit sensitive to temperature, but more sensitive to (re)loading a program which turns on the xtal/PLL clock, when
    they wobble around for a second or too. The matching ~7kHz baseband is on the supplies (5V and VIO) too
    once the P2 is up and running, haven't probed the 1.8 Vdd yet.

    The cluster of sharp peaks on the left about 8kHz off the main peak is interesting too, though that might be some
    other source of 80MHz not the P2 at all as its not obviously intermodulating the main peak, or it could be from the
    20MHz crystal itself as they often have a bit of structure around the main resonance.

    I'm loading the XO pin with 1k resistor into the SA lead, which could have an influence of course, but I don't have a
    high impedance input, and other pins show the same intermodulation product around strong peaks
  • jmgjmg Posts: 13,618
    edited 2019-01-20 - 21:55:20
    Mark_T wrote: »
    VCO/PLL is on, as via:
    CON
    OSCMODE = $010c3f04
    FREQ = 160_000_000
    PUB demo | i
    clkset (OSCMODE, FREQ)


    The 7kHz peaks are unstable and seem to show wide phase noise spreading.

    Can you test just the Xtal alone, no VCO/PLL ?
    Mark_T wrote: »
    The 7kHz peaks are unstable and seem to show wide phase noise spreading.
    Suggests something like motor-boating in the clock generation circuitry perhaps?
    They are a bit sensitive to temperature, but more sensitive to (re)loading a program which turns on the xtal/PLL clock, when
    they wobble around for a second or too.
    I 'd think motor-boating would be far more dramatic, It does not appear to loose frequency lock at all, just have phase effects added on top.
    7kHz is just wierd, as that's miles away from any action.

    That few-seconds comment is interesting, as I've noticed a definite settling time on the HC4046 phase, see below. (20Mhz XO compared with SysCLK/8==20MHz)
    I think the either-slope effect (1st is up, 2nd is down) is just either triangle effect


    With a 160M/8 compare there will be 8 possible phases, and multiple resets/retries are needed to get a mid-range plot. Near the rails are best avoided, as the phase detector triangle-wraps.
    At 20Mhz PFD, one triangle slope is 180', or maps to 25ns rail-rail analog timing display (so fractions of ns should be easy to see here ).

    The hard to explain feature here, is the large phase change and long delays. See in plotB, it starts clipping 3v3 and then warms (eventually) all the way down to 1V region

    A quality PFD should lock with quite stable phase, leaving just propagation changes as part warms.
    The above phase walk appears to be well over 10ns, approaching 20ns, and that's huge in temperature alone.

    I'd expect delays to be single-digit ns, and changes in delays to be smaller still, but maybe Chip's string of buffers in the Xtal path adds delays.
    I wonder what Spice says about P2 XO to Pin phase changes vs temperature ?


    Notice also the width of that phase noise, quietens down somewhat as things warm up (at least it does in plot B & generally), also hard to explain.
    Maybe that's just the close-to-rails effect, as the noise is showing signs of clipping -ve there.
  • TubularTubular Posts: 3,608
    edited 2019-01-21 - 10:31:53
    Today Rogloh lugged his Sony G520 (CRT) over, and I brought in my SLR to take some screen shots driving it up near its limit of 2048x1536 60Hz (210 MHz dot clock using RB1 timing with a slighty extended HSync pulse length). The camera shutter is locked at 1/60sec

    There are quite a few pictures so i've posted the images to a to dropbox directory. About half way through the testing we switched from white to green pixels so there was less 'phosphor confusion'.

    Initial tests were done with white lines 32 pixels apart in X direction, and 20 lines apart in Y direction. The horizontal line rate is around 95 kHz, and during wobbling there are often about 1.5~3 cycles per vertical 20 lines, giving a ~16 to 32 kHz wobble. Very roughly.

    Most of the photos show a wobble amplitude smaller than previously, but some of the white captures show a really extreme amplitude of half a 32 pixel wide cell or perhaps more. PLL divide ratio was 32 and multiplication 336 to help bring on wobbles.
    4592 x 3056 - 6M
  • That shows up the problem nicely!
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  • jmgjmg Posts: 13,618
    Tubular wrote: »
    Most of the photos show a wobble amplitude smaller than previously, but some of the white captures show a really extreme amplitude of half a 32 pixel wide cell or perhaps more. PLL divide ratio was 32 and multiplication 336 to help bring on wobbles.
    Nice plots, turned the CRT into a vertical axis scope, that's quite close now to what my HC4046 XOR phase detector output shows.

    What was being varied in these tests ?

  • Was only varying temperature, with a halogen floodlight, to bring on the wobbles.

    I guess the other variable is the PLL divisor - we were using /32 here.

    I couldn't get /2 to wobble. I will try again today, perhaps /2 is robust enough to not be affected.

  • jmgjmg Posts: 13,618
    Tubular wrote: »
    Was only varying temperature, with a halogen floodlight, to bring on the wobbles.

    I guess the other variable is the PLL divisor - we were using /32 here.
    So Divisor was always /32 and only temperature changed ?

    Wow. Some of those plots look quite stable, and some are, well, terrible.
    Were there zones of worst, or was higher temperature worst ?

    Can you output a XO related frequency on a pin, and scope compare the 2 & see if the relative time correlates to the jitter ?
    At 210MHz, I guess that's 10MHz, so trigger on the 10MHz and the 20MHz XO will be (nominally) some fixed phase from that

    Here, I have seen a fairly significant >10ns change in relative skew with modest heating, so I wonder if that relative skew is related to those bad-zones that have been observed before ?
    That's a number of sysclks, and it might be moving the sensitive analog PLL stuff across SysCLK edges. I'd expect one sysclk edge to be noisier than the other.
    The skew seems temperature linear, it just slowly moves phase as the chip heats up.

    Is there a P2D2 you can run the same test on ? (the CMOS clock drive on that may skew less ?)
    A P2D2 with a 20MHz CMOS oscillator would be even better, as it keeps PLL exactly the same.
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