How is a Microcontroller’s Language Made?

I have been bugged by this for ever. When you write PBASIC, the Stamp interprets it using whatever assembly language the interpreter PIC runs. But when you run the assembler language, what happens? Does it trigger a series of transistors inside the chip? And how is the assembler language made?
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Comments

  • It has it's own instruction set built in. Look up the data sheet for the PIC16F5X.. When you load a program it saves the code to the built in flash memory. When you power it on the PIC loads the saved code and runs it.
    That's simplified explanation in a nut shell.
  • If you really want to know, then check out this two part class and you will have a good understanding:

    https://www.coursera.org/learn/build-a-computer

    I think that the first half will answer your question. If you really enjoy this, then you can later get into FPGAs and build your own. Many more people seem to have an interest lately. I think that it's due to open source tools becoming available.
  • https://www.amazon.in/Code-Language-Computer-Developer-Practices-ebook/dp/B00JDMPOK2

    That book starts from first principles. Good read for you, but it may take a bit to really get going. If you can, power through some. It pays off.

    In general, the assembly language gets made as a direct artifact of how the CPU gets made.

    Instructions map to circuits that do the work. Some common things are always there: MOV, ADD...

    Other things end up just happening as the design develops and ways to control it, or get work, data, to and from it become sensible.

    There are also instruction sets that get mapped out ahead of time too. RISC V is one of those. CPU designs get made to perform the work the instructions require.

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • Agreeing with @potatohead's book proposal. As a coincidence, I started to read this 2 days ago
    - Thomas Vikstrom (banjo)
    Location: A hop from the longest bridge in...Finland
  • I thought it a fun and enlightening read. Enjoy!
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • @potatohead
    After the built in code stage, the IDE just has to read the keyboard and compile the right byte patterns?
    What is with the wierd currency on the book’s webpage?
    Returning to Spin after two months of not coding micros at all, forgetting to use :=
  • What is RISC V?
    Returning to Spin after two months of not coding micros at all, forgetting to use :=
  • RISC V is an open specification of a processor instruction set. https://riscv.org/
    It's a very simple instruction set that, being open, can be used by anyone to create a processor, in actual silicon chips or as FPGA logic designs. You can read the technical description here:https://riscv.org/specifications/ It's short a sweet and pretty easy to understand.

    Being an open specification it already has a lot of support from tool creators, like C compilers (GCC/Clang), Pascal (Free Pascal) etc, etc.

    So far there are few actual RISC V chips one can buy. For example https://www.sifive.com/boards/hifive1 and
    https://www.cnx-software.com/2018/10/19/kendryte-kd233-risc-v-board-k210-soc-machinve-vision/

    This past year or so I have been busy learning Verilog and getting started designing my own RISC V processor core to use in in FPGA.

  • It stands for reduced instruction set.
  • I live a sheltered life. What is FPGA?
    Returning to Spin after two months of not coding micros at all, forgetting to use :=
  • Heater.Heater. Posts: 21,213
    edited 2019-01-13 - 16:58:58
    Good question.

    FPGA = "Field Programmable Gate Array"

    Basically an FPGA is a chip full of digital logic that is configurable to create all manner of logic designs. Before you configure it it does nothing. You can reconfigure the same chip many times for different logic designs.

    This all sounds horribly complex but at the end of the day one can use the software tools provided by the FPGA vendors to create your logic design. Either graphically, drawing AND gates FLIP-FLOPS and such, or by writing a logic description in a high level language like Verilog or VHDL. That's more like writing regular programs.

    The biggest FPGA vendors are Xilinx: https://www.xilinx.com/products/silicon-devices/fpga.html and https://www.intel.com/content/www/us/en/fpga/devices.html

    Lattice have some nice cheap FPGA that one can configure using completely Open Source tools:https://www.latticesemi.com/icestick

    Typically a hobbyist would not by the chips directly but rather get a little development board. They can be very cheap, see that IceStick above.

    When I was 14 I was tinkering with digital logic designs by soldering together lots of TTL logic chips: https://en.wikipedia.org/wiki/Transistor–transistor_logic. It's luxury today to be able to build complex logic with out all that hardware expense and soldering!

    There are loads of FPGA turorials on the net now a days:
    https://www.allaboutcircuits.com/technical-articles/fpga-tutorial-step-1-the-development-environment-and-hello-world/
    https://numato.com/kb/learning-fpga-verilog-beginners-guide-part-1-introduction-a7/?utm_expid=.7ZBm96RhTSyo2rg6tZl_vQ.1&amp;utm_referrer=https://www.google.com/

  • potatohead wrote: »
    Instructions map to circuits that do the work.

    That speaks volumes. Thanks for the explanation. I think another word for "instruction" is 'opcode'.
    I think I've heard that the P2 will be software based. By that explanation the P1, in contrast, has an instruction set that maps to hard wired circuits.
    I'm not quite ready for an explanation of how the P2 architecture differs from that of the P1. I'll be watching and learning from the sideline.
    Larry

    If the grass is greener on the other side...it's time to water your lawn.
  • "software based" usually refers to microcode where what looks like a fairly complex computer like an older Pentium is created using a very fast and simple microcomputer running fixed code from an on-chip ROM that interprets what the user sees as the instruction set. IBM used this very effectively in their System 360 line of computers. The smaller slower cheaper models were all implemented with microcoded processors while the faster more expensive models were implemented all in hardware. All of the models had the same instruction set.

    Both the P1 and P2 are hardware based (using your terminology).
  • Mike Green wrote: »
    "software based" usually refers to microcode where what looks like a fairly complex computer like an older Pentium is created using a very fast and simple microcomputer running fixed code from an on-chip ROM that interprets what the user sees as the instruction set. IBM used this very effectively in their System 360 line of computers. The smaller slower cheaper models were all implemented with microcoded processors while the faster more expensive models were implemented all in hardware. All of the models had the same instruction set.

    Both the P1 and P2 are hardware based (using your terminology).

    "Microcode". That helps.
    I know SPIN produces 8-bit bytecodes that are fetched by the cog from the hub and executed in assembly. SPIN instructions can't be defined in terms of clock cycles because you can't predict where the hub pointer will be.
    I'm getting closer. Thanks Mike.
    Larry

    If the grass is greener on the other side...it's time to water your lawn.
  • You may be able to specify a range of clock cycles and worst case for a few simple Spin bytecodes that access hub memory only a few times. It's a lot of work and I haven't gone through the Spin interpreter with that kind of attention, but I have done it with some of my own code.
  • AwesomeCronkAwesomeCronk Posts: 806
    edited 2019-01-14 - 13:22:20
    So, the propeller has a boot loader, is it written in assembly? Can it be changed, or is it hardwired?
    Returning to Spin after two months of not coding micros at all, forgetting to use :=
  • In PASM yes, its in ROM so cannot be changed.
  • AwesomeCronkAwesomeCronk Posts: 806
    edited 2019-01-14 - 15:02:45
    Ok. Could a program be written to function as a boot loader, then be loaded to EEPROM? Then the boot loader loads the other bootloader, which then copies another program to internal ram?
    Returning to Spin after two months of not coding micros at all, forgetting to use :=
  • Mike GreenMike Green Posts: 22,921
    edited 2019-01-14 - 15:40:04
    Yes, a program could be written as a boot loader and stored in EEPROM. This has been done several times. The Propeller Backpack does this to load over a half duplex serial line. The Activity Board WX does this to load over WiFi. FemtoBasic does this to load from an SD card file. The SimpleIDE loader uses a 2 stage loader for C/C++ programs. Here's one example that loads from an SPI Flash memory file. The boot loader stuff starts around line 550. You'd need to add a calling routine that provides a starting address in flash memory for the program file to be loaded.
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