Thoughts on simulating the Propeller microcontroller, in software?

Is anyone interested in simulating the Propeller microcontroller? I recently came across a program called Verilator that translates Verilog into a C++ program that simulates the operation in software. It supports a direct programming interface that lets traditional C++ code communicate directly with Verilog code, which would make it easy to set and read states, registers, and memory in the simulated processor.

The Verilog files for the Propeller 2 aren't available publicly, but they are for the Propeller 1, so it should be possible for anyone to use Verilator, to make a Propeller 1 simulator. It would take some work adding a few direct programming interface lines in the Verilog files, switching to purely Verilog memory blocks, and writing a C++ interface.

If anyone gets the Propeller 1 simulated with Verilator, we could make a build using the Propeller 2 Verilog files, and publish the compiled output, so anyone could simulate the Propeller 2.

Comments

  • That would be cool. I still have fond memories of using the Gear GEAR Emulator to get started with the propeller chip(P1). :)
  • I am not sure how you would simulate smartpins or even digital ones, what would be a C++ based P2 good for?

    And there is also spinsim simulating a P1 or a P2. Not sure how complete.

    Since Verilator can create C++ out of Verilog, I think that there is software out there creating the Verilog out of the Verilator output again, that might be risky.

    Also the analog part of the P2 is not done in Verilog, as far as I know, thus Verilator will have a hard time to compile the P2 Verilog I guess.

    Doing that for the P1 might be possible, but there is already GEARS and spinsim, so why?

    Let them buy the real chips...

    Mike
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  • jmgjmg Posts: 13,928
    Is anyone interested in simulating the Propeller microcontroller? I recently came across a program called Verilator that translates Verilog into a C++ program that simulates the operation in software. It supports a direct programming interface that lets traditional C++ code communicate directly with Verilog code, which would make it easy to set and read states, registers, and memory in the simulated processor.

    The Verilog files for the Propeller 2 aren't available publicly, but they are for the Propeller 1, so it should be possible for anyone to use Verilator, to make a Propeller 1 simulator. It would take some work adding a few direct programming interface lines in the Verilog files, switching to purely Verilog memory blocks, and writing a C++ interface.

    If anyone gets the Propeller 1 simulated with Verilator, we could make a build using the Propeller 2 Verilog files, and publish the compiled output, so anyone could simulate the Propeller 2.

    I guess it all comes down to speed ?

    I understand the Atmel AVR simulator, uses this approach of derived from the verilog.
    The plus aspect, is you should simulate all wrinkles, down to being cycle accurate.
    msrobots wrote: »
    I am not sure how you would simulate smartpins or even digital ones, what would be a C++ based P2 good for?

    Smart pins are verilog, so they should simulate fine.
    DACs will not simulate within the Verilog-compiled-Block, but they can pass to a Scope type display, if someone wanted.

    There is a place for both Final Silicon Testing, and Simulators, but those simulators need to be easy to use, and fast.

    Conversely, for Silicon testing to be able to compete, it needs to also be complete, and fast.
    P2 has silicon hooks to allow good 'almost invisible' debug, but the GUI side of that is still 'to do'.

    The newest Ardunio's have Atmel Debug firmware and bridge silicon, allowing access to Step/Break/Watch levels of code inspection.
    That's pretty much the industry norm of all the big players.


  • Personally I have always thought of an Emulator needing speed when you want to run the entire project, and a Simulator more for concept to prove out pieces of code within a project.

    Now days I program strictly in Assembly (perhaps old school, but honestly I prefer it that way). The tools however seem to be much nicer than they were 30 years ago, but my programming technique has also matured over that time as well. :-)


    Beau Schwabe --- Robotics applications- PCB design, embedded software, and mechanical
    Oklahoma Robotics -

    www.Kit-Start.com - bschwabe@Kit-Start.com ෴෴ www.BScircuitDesigns.com - icbeau@bscircuitdesigns.com ෴෴

  • P1v on Verilator has been done.

    forums.parallax.com/discussion/comment/1415823/#Comment_1415823
    The hub ram now loads from a file, significantly reducing the startup time. I also pre-load the booter into cog ram. That was easier than inserting the modified booter back into the rom image. :smile: The application shouldn't be able to tell the difference.

    It took 4m16.791s to simulate 1 second. That's 1/256 real time. I used Retronitus as a stress test. I've simulated 9 seconds so far, sounds great!

    I'm probably going to go back to P1V on iCE40 now. But, now I'll know that my verilog is good! :cool:

    P2 will likely run much slower. Would such a simulator be useful? Maybe.

    Who knows how much the original verilog would be exposed by the Verilator code output or even a compiled library of it.


    James https://github.com/SaucySoliton/

    Invention is the Science of Laziness
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