Has a P2 Symbol Been Made For KiCAD, FREECAD, Eagle, ETC.?
AwesomeCronk
Posts: 1,055
in Propeller 2
I am worried for new developers of P2 boards having to each make their own symbol/footprint. I myself don't see a P2 symbol for KiCAD.
Comments
https://docs.google.com/document/d/1UnelI6fpVPHFISQ9vpLzOVa8oUghxpI6UpkXVsYgBEQ/edit
There are tools for quickly defining KiCAD schematic symbol libraries here:
http://kicad.rohrbacher.net/quicklib.php
Well, not quite 'standard' as the Exposed Pad of 9.5mm on P2, is not present in a standard TQFP.
The P2 package is more correctly called TQFP100EP
KiCAD has a
TQFP-100_14x14mm_Pitch0.5mm,
which has no paddle, and it also has
TQFP-100-1EP_14x14mm_Pitch0.5mm, with a 5mm default paddle, that you can quickly size-edit to be a 9.6mm PCB size for the 9.5mm exposed pad.
I checked and Peter used 10.287mm on P2D2 ?
.. but not in more portable formats yet ?
P-CAD export from Diptrace should import into KiCAD. I can check, as soon as a P-CAD exported version is posted.
Please let me know if they run.
Was that a netlist export, or a complete design export ?
Both load ok, just one warning on Eagle pathway, but that seems to include dimension details PCAD has omitted. PCAD load is a bit slower than Eagle, but not something you repeat often.
See screenshots, I'll check fill and DRC next.
In KiCad, the via padstacks are the same on all layers.
Addit: hmm, I think these were maybe blind vias, that did not quite translate across. Blind vias usually add quite a bit to a board cost, and this is not really a dense board design.
KiCad expects those to be on adjacent layers only (thinnest material?), whilst Diptrace has tagged microvia with more-layer reach.
Editing all the microvias to thru, and then change of the violating vias to blind L1-L2 (mostly, tho there are a handful of other layers blind vias too... ?!)
Now has errors down to 6, and those are due to inner-layer padstacks issues, or other layer-pair blind vias...
Clearance had to go to 0.05mm to pass, but only for rare/accidental looking errors.
Some traces have relied on removal of copper rings on inner layers, and clearance to drill alone.
KiCad does not default to doing that, and the GUI does not support explicit layer defines, but I did find
Default is *.Cu - means all copper layers.
Edit manually to top.bottom saves as (layers F&B.Cu *.Mask), and gerbers show that has no L2,L3 ring info, just L1,L4
Just a few parts fail on this error, the FAN & GND mounting holes, and one 12W header.
I also notice the 3v3 LDO regulator footprint, does not quite import correctly, in either export case.
Addit: Existing KiCad footprint UDFN-4_1x1mm_Pitch0.65mm, I think is very close to that regulator.
Err, yes, that's exactly what this does. (KiCAD has direct import of PCAD and Eagle files, both come across with 99% integrity.)
See my posts and pictures above, of issues with two possible pathways into KiCAD.
I found some issues around Design Rules, Copper pour ordering, and naming conventions around microvia and blind vias.
With a 2 hop process, it's less clear where details of funny footprints like the 3v3 regulator get dropped.
EDIT: This was the only error.
End of export errors.
KiCAD does support oval holes, so that is easily patched.
Which parts have non-round inner layer pads ?
KiCAD does not naturally support inner layer padstacks, but I did manage to knock the unusual J210 into submission by manually inserting stacks onto all routed layers (and omitting from unrouted layers).
Not sure if that was a custom part in DipTrace, or if it automatically removes inner, unused annular rings ? Seems a bit custom ?
Even tho KiCAD does not formally support inner layer stacks (in my not so recent version, some months old) it does mark a pin with a white 'x' if you have a trace and no annular ring.
(and then tags it with a bad error message...)
Gerbers and fills do look ok at the end.