HyperRAM breakout for P2-EVAL-ES
RJSM
Posts: 68
in Propeller 2
Here’s a small HyperRAM breakout board I’ve developed for the P2-EVAL-ES. I just plugged my earlier OSHPark HR carrier (the purple board) into a new PCB that provides access to P11…0 on the P2-EVAL. There’s also a WS2812B on there to serve as a cool status indicator.
I’m using LabVIEW to communicate with my EVAL at 3Mbaud. Presently the P2 is running @ 240 MHz (no thermal issues at all). The code accesses the 8 megabyte HR chip as 65536 x 128 byte blocks. The HR read and write routines that transfer these 128 byte blocks between HUB RAM and HR each execute in ~1500 nsec, equating to a transfer rate of 85MB/sec. I’ve not tried to push my setup beyond 240 MHz as I don’t currently have any cooling - but so far everything is looking good.
Its summer down here in Oz so progress now takes a back seat to some holiday time - but I do plan to post code and design files in case others wish to populate their own boards. I think this will likely be some time after our next Melbourne P2 catch-up – Jan 10th ??
I’m using LabVIEW to communicate with my EVAL at 3Mbaud. Presently the P2 is running @ 240 MHz (no thermal issues at all). The code accesses the 8 megabyte HR chip as 65536 x 128 byte blocks. The HR read and write routines that transfer these 128 byte blocks between HUB RAM and HR each execute in ~1500 nsec, equating to a transfer rate of 85MB/sec. I’ve not tried to push my setup beyond 240 MHz as I don’t currently have any cooling - but so far everything is looking good.
Its summer down here in Oz so progress now takes a back seat to some holiday time - but I do plan to post code and design files in case others wish to populate their own boards. I think this will likely be some time after our next Melbourne P2 catch-up – Jan 10th ??
Comments
That comes to appx 98ms repeat rate ? Did you try slowing that down, to see when/if refresh issues ever bite ?
The data specs a tight 4us for tcms, and is vague on if refresh is one-click-per-cms, or if refresh runs all the time when deselected.
The latter would mean more choice in when to pause for refresh.
Re the refresh question I did investigate that back in FPGA emulation days and my recollection is that it appears refresh runs all the time.
Yes, 10th Jan is the day... looking forward to it.
3v3 (BLL suffix) P2 ports cannot manage 1v8.
Impedance drive and speed may also be affected
I thought Chip ran some tests, and the level shifters could not manage 1v8 VIO ?
As you say, even if they could reach 1v8, the speed would be very poor.
Separate to VIO, there's still a way to use the DACs to drive 1v8 output at full speed (2ns settling dacs), and a corresponding 'threshold input' (using slow dac feeding into input comparator) to achieve 1v8 inputs.
Testing this with Hyperram would really validate this 'soft-vio' aspect of P2, since it would simultaneously push the clock, verify read write data integrity etc
You did an awesome work with those Hyper things!
Apart from the sufix of the chips (BLL or ALL) one chooses to mount on them, the simple existence of the breakouts will enable the validation of a lot of concepts and many kinds of tests.
These will include the Hyperflash and the duals too (Hyperflash + Hyperram).
Eager to take a look at the software you did.
Henrique
I'd love to try this out beforehand since I have designed a one onto my new P2D2.
Yes I did the PCB's and assembly myself. I have a Beta Layout reflow controller and an el-cheapo Kmart toaster oven. The former was pretty pricey but its been great for doing numerous SMT projects; many of the most recent have been instruments built with the ESP32 while eagerly awaiting arrival of the P2. I've got some plans to team the ESP32 up with the P2 down the track - but that's another story.
Here's the link to the controller : https://uk.beta-layout.com/estore/order_product_details.html?wg=1&p=613 - but from what you've posted I reckon you've got a very good smt setup already.
Soldering the BGA was just a matter of very carefully placing the package onto the PCB using the silkscreen outline for placement. I did some reading about appropriate pad sizes to properly accommodate the balls and had a few initial failed attempts - but it doesn't appear to be too problematic. The chip seemed to go down onto those OSHPark gold plated pads quite nicely. Obviously a next version PCB would be a single board design - really not much work at all - but I'm hoping Parallax will do one first ! Would be great to see HR accessible from TAQOZ too.
I am out of town now (we have escaped the Melbourne 42C heat today to head down the coast till mid next-week) but when I get back i'll check my PCB stocks. The green board was a JLCPCB job ($2 for 10 boards) and I should still have 9 of these left over - could send one up to you in Brisbane. The OSHPark one I'm not sure - I might have 1 left - but i'll check that too. I have a couple of dozen HR chips as well. There's a 16MB version that I bought a while back too but have not tried that out. More than happy to help in any way I can once back in town.