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Breakouts for P2 Eval — Parallax Forums

Breakouts for P2 Eval

I know Parallax is coming out with add on boards for P2 EV.
But, I just turned the one I did to add HyperRam to P123 into a board for P2 EV.
Mostly because I already have a stencil and I know the design works...

Thought I'd share... You can only connect one side or the other.
One side gives HyperRam and a few servo headers.

Other side gives QPI Flash, uSD, regular flash and two USB ports.

Since I'm at it, doing my own VGA breakout too. Still thinking about what else to add to this one...
VGA only uses 5 of 8 P2 pins...
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Comments

  • kwinnkwinn Posts: 8,697
    edited 2018-12-29 15:13
    Rayman wrote: »
    I know Parallax is coming out with add on boards for P2 EV.
    But, I just turned the one I did to add HyperRam to P123 into a board for P2 EV.
    Mostly because I already have a stencil and I know the design works...

    Thought I'd share... You can only connect one side or the other.
    One side gives HyperRam and a few servo headers.

    Other side gives QPI Flash, uSD, regular flash and two USB ports.

    Since I'm at it, doing my own VGA breakout too. Still thinking about what else to add to this one...
    VGA only uses 5 of 8 P2 pins...

    Connect them along with GND and 3.3 or 5V to a 6 pin header so they can be used for things like audio, pwm, serial i/o, keyboard, mouse, etc. The unused pin could be cut/left off so the connector could not be reversed.
  • Rayman wrote: »
    I know Parallax is coming out with add on boards for P2 EV.
    But, I just turned the one I did to add HyperRam to P123 into a board for P2 EV.
    Mostly because I already have a stencil and I know the design works...

    Thought I'd share... You can only connect one side or the other.
    One side gives HyperRam and a few servo headers.

    Other side gives QPI Flash, uSD, regular flash and two USB ports.

    Since I'm at it, doing my own VGA breakout too. Still thinking about what else to add to this one...
    VGA only uses 5 of 8 P2 pins...

    Add audio, and one empty DAC.
  • RaymanRayman Posts: 13,799
    Good ideas, thanks.
    Was just looking at this ESD chip for VGA:
    http://www.ti.com/product/tpd7s019?qgpn=tpd7s019

    It also does level shifting on DDC lines.
    Interesting to think about, but don't think we need ESD protection or DDC, right?
  • Do you have an opinion yet about EVE2 vs driving LCD pins direct? What about a 40pin FPC and 6pin FPC for touch.
  • Rayman wrote: »
    I know Parallax is coming out with add on boards for P2 EV.
    But, I just turned the one I did to add HyperRam to P123 into a board for P2 EV.
    Mostly because I already have a stencil and I know the design works...

    Thought I'd share... You can only connect one side or the other.
    One side gives HyperRam and a few servo headers.

    Other side gives QPI Flash, uSD, regular flash and two USB ports.

    Since I'm at it, doing my own VGA breakout too. Still thinking about what else to add to this one...
    VGA only uses 5 of 8 P2 pins...

    well PS2 Keyboard/mouse comes to my mind and would make sense with VGA.

    Mike
  • RaymanRayman Posts: 13,799
    P2 should be about perfect for 4.3" and smaller displays.
    5" and higher, I'd have to think about it...
    EVE2 is great for GUI applications. Wouldn't work so well when fast, dynamic full screen updates are needed...

    I do feel the need to make a 4.3" LCD board now, especially since you reminded me that don't need external ADC chip for resistive display...
  • RaymanRayman Posts: 13,799
    I'm hoping to only use USB keyboard and mice with P2...
    Hopefully garryj can get it working with p2 eval (and also find a way to get it all in one cog).
  • Not me. PS2 is so dead simple and lean.

    Will be nice to have the option, do not get me wrong. Being able to use other input devices may make sense, as might storage.

    As long as there are reasonable adapters, I will use the simlle, low resource option for keyboard and mouse.

    Wil be super interesting to see what tradeoffs are worth what as people ramp up.
  • jmgjmg Posts: 15,140
    Rayman wrote: »
    I know Parallax is coming out with add on boards for P2 EV.
    But, I just turned the one I did to add HyperRam to P123 into a board for P2 EV.
    Mostly because I already have a stencil and I know the design works...

    Thought I'd share... You can only connect one side or the other.
    One side gives HyperRam and a few servo headers.

    Other side gives QPI Flash, uSD, regular flash and two USB ports.

    Since I'm at it, doing my own VGA breakout too. Still thinking about what else to add to this one...
    VGA only uses 5 of 8 P2 pins...

    Maybe allow footprints for 1 or 2 of these ?
    https://www.electrodragon.com/product-tag/ram/
    https://lcsc.com/product-detail/RAM_Lyontek-Inc-LY68L6400SLIT_C261881.html

    Those are SO8, PSDRAM, so they have refresh rules similar to hyperram, but are not DDR and not BGA

    One idea was to connect 4 of these to a 16W LCD BUS, and use 2 carefully paced clocks, one for LCD one for PSRAM.
    RAM->LCD is set RAM address then any LCD command, then clock both. Gaps are used for writes.

    There is also
    http://www.jeju-semi.com/Products/OctaRAM
    they claim M/P on JSC64SSU8AGDY-75I (24B BGA 6x8mm), but data is elusive.
    There is also Macronix part code MCP = MX65L12A64AA, 512Mb OctaFLASH 64Mb OctaRAM x8 x8 3V 6x8mm 24-TFBGA - maybe has 2 chip selects ?
  • jmgjmg Posts: 15,140
    Rayman wrote: »
    I do feel the need to make a 4.3" LCD board now, especially since you reminded me that don't need external ADC chip for resistive display...
    Another option would be to add headers for the LCDs that appear when you search eBay for 128M SPI LCD
    That has a subset of RaspPi 40W as 10w + 4w female box headers, for power and SPI ends.

    To hit 128MHz the leads would need to be sort, given the comments already around SD track lengths and MHz impacts.

  • RaymanRayman Posts: 13,799
    edited 2018-12-29 20:35
    It's an interesting option. But, we have loads of I/O pins now... Plus, I still have a large stash of 4.3" displays...
  • jmgjmg Posts: 15,140
    Rayman wrote: »
    It's an interesting option. But, we have loads of I/O pins now... Plus, I still have a large stash of 4.3" displays...

    I see two main mechanical designs - one where the P2 is right behind the LCD and direct parallel connect is fine, and another where the LCD(s) is remote from the P2, and a serial display cuts cables.

    Longer term, we can imagine LCD modules like that CPLD one, use a P2 instead, for serious flexibility ;)
  • Ozprop and I still have your prev 4.3" effort that was used with P1.

    Those displays were nice and bright, and ideaal from a ram usage viewpoint. It'd be great to see them up and running with P2
  • RaymanRayman Posts: 13,799
    edited 2018-12-29 23:48
    the 4.3 on P2 is going to be a lot of fun
    Just don't want to use a ton of pins...

    Think I can use 3 octal D flops to latch in 24-bit color...
    Maybe something like this: SN74LVC574A
    Then, can just use one edge of eval board...

    Max dotclock is 15 MHz. Seems like would have all day with P2 at 300 MHz...
  • +1

    Oh yes, I would buy one

    Mike
  • potatoheadpotatohead Posts: 10,253
    edited 2018-12-30 03:06
    Yeah, the latch makes great sense at 15Mhz. Plenty of time to save the pins.
  • jmgjmg Posts: 15,140
    edited 2018-12-30 09:01
    Rayman wrote: »
    ...

    Think I can use 3 octal D flops to latch in 24-bit color...
    Maybe something like this: SN74LVC574A
    Then, can just use one edge of eval board...

    Max dotclock is 15 MHz. Seems like would have all day with P2 at 300 MHz...

    You might mange just 2 latches, and feed the other 8 bits straight thru, with careful timing.
    Tpds,Tpdh look to be 10ns, for a 15MHz period of 67ns

    Streamer does not mention 24b mode, and it's not clear if P2 can stream HUB -> LUT at fp/3, or fp/4, and then LUT.24 or LUT.32 -> 8 pins at fp ?

    A MUX of LUT.32 -> 4 x 8 @ fp, could help the reduced-latch design, ie by repeating the last value 8 bits in LUT, it gives 50% of the LCD timing for Tsu/th

    I also see there are bus-hold and series terminated D-Latches, but more fringe parts :
    SN74LV574A is listed as cheapest at TI.com, then SN74LVC574A, SN74AHC574,SN74HC574

    The Nexperia 74AHC574 has Schmitt triggers on all pins, and does not have the very high drive of LV/LVC, so has less ringing. Nexperia AHC parts spec at 125MHz typ

    Looking more at the clocks, & data flows, the AHC377 appeals, (alternate could be LVC377) as it has a Data Enable, which allows this scheme, where LCD_DE == 377_DE
    and separate clocks/clock gating are avoided.
    Cascade D-FF AHC377.H & AHC377.L to make a simple FIFO
    P2 CLK __________/====\____/====\____/====\____/====\____/====\____/====\____/====\____/
    P2 BUS ________111111111/222222222/33333333/3333333333/111111111/222222222/333333333/333333 Repeats 3 & 3
    LCDCLKN_377DEN _____________/===================\__________________/====================\_________  if =\_ possible
    LCDCLK        ==============\___________________/==================\____________________/========= if needs _/=
    AHC377.L       1111111111112222222222222222222222222222221111111111222222222222222222222222
    AHC377.H       2222222222221111111111111111111111111111112222222222111111111111111111111111 Loads 1,2 into latches
                               ^New      ^Hold     ^Hold     ^New      ^New      ^Hold      ^Hold 
    LCD                                            ^--Load 1.2.3 377+P2.BUS
    
    (fixed 377 has active low Enable)
    Or, a CPLD could do this too...CPLD could create the LCDCLK/377DEN as needed.


  • RaymanRayman Posts: 13,799
    The 2-stage fifo is a good idea. I'll just put two SN74LVC574A in series and feed lower 8-bits directly from P2 to LCD. Think there's just enough pins to pull this off:
    8-pins color
    1-pin fifo
    3-pins vsync, hsync, de
    1-pin BL&DON
    2-pins touchscreen
    1-pin pixelclock
    
  • jmgjmg Posts: 15,140
    edited 2018-12-30 20:51
    Rayman wrote: »
    The 2-stage fifo is a good idea. I'll just put two SN74LVC574A in series and feed lower 8-bits directly from P2 to LCD. Think there's just enough pins to pull this off:
    8-pins color
    1-pin fifo
    3-pins vsync, hsync, de
    1-pin BL&DON
    2-pins touchscreen
    1-pin pixelclock
    

    Here is a variant that uses a lower CLK frequency in a 2 phase, 4 state scheme, with 2 x x574, and a Single-Gate XOR to set the LCD polarity.
    This is both SW and HW compatible, should be good for 15~30MHz LCD clks, either polarity
    SYSCLK       |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   
    L.CLK   _________/===============\_______________/===============\_______________/===============\____
    P2 BUS ________aaaaaa/bbbbbbb/ccccccc/ccccccc/AAAAAAA/BBBBBBB/CCCCCCC/CCCCCCC/aaaaaaa/bbbbbbb/ 32b HW repeats cc,CC
    H.CLK   _________________/===============\_______________/===============\_________ 
    LCDCLK ____________/===============\_______________/===============\_______________/=========  =\_ == L.CLK
    LCDCLKN ===========\_______________/===============\_______________/===============\_________  _/= == !L.CLK
    AHC574.H       xxxxxxxxxxbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbBBBBBBBBBBBBBBBBBBBBBBBBBBBB 
    AHC574.L   xxxxxxaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAaaaa
                     ^NewL   ^NewH                   ^NewL   ^NewH                    
    LCD                                ^--Load a.b.c                   ^--Load A.B.C 
    LCDCLK is XOR gate from L.CLK, selects LCD_CLK polarity, some LCD are _/= some =\_ 
    
    
    This could prune to a 16b interface, with a single clock (uses both edges), and 1 Octal D-FF
  • Rayman wrote: »
    I'm hoping to only use USB keyboard and mice with P2...
    Hopefully garryj can get it working with p2 eval (and also find a way to get it all in one cog).

    For a non-bluetooth wireless dongle that supports mouse/keyboard and boot protocol and a P2 at 180MHz+, I'm pretty sure a single-minded host/driver mash-up would be doable in one cog.
  • potatoheadpotatohead Posts: 10,253
    edited 2018-12-30 20:04
    Cool :D

    I just picked up a little wireless Bluetooth keyboard with a mouse pad thingy. It looks a little like a game controller. When I'm close to it again I'll provide a link. But it could be really cool to work with P2. Could change my mind on USB in some occasions.
  • RaymanRayman Posts: 13,799
    Wonder what the best way to do resistive touch is...
    Guess I'll just tie up and left to 3.3V and connect bottom and right to P2 pins...
  • I used an AR1010 in a design once, it has some useful diagrams showing the read sequence
    http://ww1.microchip.com/downloads/en/DeviceDoc/40001393C.pdf
  • RaymanRayman Posts: 13,799
    I forgot how these touchscreens work for a second...
    Think I need 4 P2 pins to work it without a touchscreen controller...
    Guess I'll either go without or drop in the TSC2003 I2C controller I usually use...
  • jmgjmg Posts: 15,140
    Rayman wrote: »
    The 2-stage fifo is a good idea. I'll just put two SN74LVC574A in series and feed lower 8-bits directly from P2 to LCD. Think there's just enough pins to pull this off:
    8-pins color
    1-pin fifo
    3-pins vsync, hsync, de
    1-pin BL&DON
    2-pins touchscreen
    1-pin pixelclock
    

    If you need more pins for touch, I find this mention of DE-Only displays :

    https://hackaday.io/project/8146-ridiculous-lcd-display-hacks/log/47770-de-only-displays-no-hsyncvsync

    These parts have min/max specs for DE line and Frame pauses, that are enough to extract all sync info.
    Some parts call this HV mode / DE mode.
  • roglohrogloh Posts: 5,122
    edited 2018-12-31 04:23
    Yes I have used a similar DE mode LCD display on a P1V that required only DE, CLK and the other HSYNC,VSYNC inputs could be left floating which saves one or two pins. You just need to modify the video drivers slightly to generate the DE instead of the regular sync signals (which can sometimes be a challenge with existing OBEX drivers unless you can fit it in etc). Given the P2 video drivers right now are basically in their infancy anyway and you may need to write your own, it is probably not going to be a that big a deal to have to write one this way to begin with. With any luck the 4 channel RGBS model in the P2 can use the "sync" output pin to generate the DE signal and be high whenever the video data is valid, and a smart pin could generate the pixel clock.
  • roglohrogloh Posts: 5,122
    edited 2018-12-31 05:20
    I wonder if a nice combined board supporting both parallel LCDs and DVI-I (maybe not simultaneously) would be possible with the 16 total P2 pins available on a dual connector breakout board? Then you could potentially support DVI/HDMI and VGA and LCDs all from the same board. Maybe this is actually possible if you repurpose the 5 pins normally assigned to analog VGA for LCD control etc, and share the 8 data bits for either HDMI/DVI, or LCD with the extra latches.
  • RaymanRayman Posts: 13,799
    edited 2018-12-31 16:06
    I remember that one of my displays will work in DE mode, but don't remember which one... Might be the 4.3", not sure... Tried searching the forum, but can't find it...

    Tried again and found it, it's the 3.5" that has DE mode :(
    It's OK, I have plenty of TSC2003 chips around...
  • RaymanRayman Posts: 13,799
    Got some boards on order...
    Here's the 4.3" TFT board (screen grabs and eagle source attached).
    1535 x 1158 - 36K
    656 x 944 - 93K
  • RaymanRayman Posts: 13,799
    Here's the VGA + Audio + Newhaven EVE2 connector
    789 x 965 - 96K
    1948 x 807 - 28K
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