Comparator mode testing

ozpropdev · 2018-12-08 11:27

Chip
I've been testing the comparator modes in P2 and I have a question.

PinA mode test.
A test ramp is fed into PinA(#8). I then read the INx for the pin
and output the comparator state to anoher pin(#16). This works fine.
Here's the scope capture

PinB mode test.
Further tests put the ramp into PinB(#9) with PinA(#8) set for output.
The comparator state is also read from INx and output to pin #16.
This also wotks fine for both %1110 and %1111 modes.
Here's the two scope captures.

My question is the Pad IO table shows options for PinA output while PinA is used
as the comparator input. This seems to be a invalid configuration.
Am I missing something here?

Pad IO modes

M[12:0]		Input		PinA Output	CIOHHHLLL	OE	DAC	ADC	ADC mode	COMP
=============================================================================================================
1100_CDDDDDDDD	PinA > D	Out,1k5		C00001001	Dir	0	0	-		A>D
1101_CDDDDDDDD	PinA > D	!Input,1k5	C01001001	DIR	0	0	-		A>D
1110_CDDDDDDDD	PinB > D	Input,1k5	C00001001	DIR	0	0	-		B>D
1111_CDDDDDDDD	PinB > D	!Input,1k5	C01001001	DIR	0	0	-		B>D
=============================================================================================================

Here's my PinB test code

'%1111 mode (PinB > D, !Input)

dat		org

		wrpin	dacmode,#4		'ref out
		dirh	#4

		setbyte	compmode,#$df,#1	'threshold
		wrpin	compmode,#8
		dirh	#8
	
		rep	@loop,#0
		add	pa,#1
		setbyte	dacmode,pa,#1
		wrpin dacmode,#4		'set dac value
		testp	#8 wz
		drvz	#16			'comparator state
loop

dacmode		long	%0000_0000_000_10100_00000000_00_00000_0

compmode	long	%0000_0000_000_1111_000000000_00_00000_0

evanh · 2018-12-08 14:42

Here's my write up of the comparator config. I've tried to clarify the driving detail for each line in the config. In all cases there is a 1k5 series resister in the loop:

	%11_VV_CDDDDDDDD = COMP_DAC comparator mode
		DIR enables PinA digital output
		%VV = Comparator config
			00: IN = PinA > D, PinA driven by 1k5R from OUT
			01: IN = PinA > D, PinA driven by 1k5R from !IN
			10: IN = PinB > D, PinA driven by 1k5R from IN
			11: IN = PinB > D, PinA driven by 1k5R from !IN
		%DDDDDDDD = DAC level for internal analogue compare

evanh · 2018-12-08 14:44

Here's all the pad IO config write up I did - https://forums.parallax.com/discussion/comment/1452036/#Comment_1452036

There is still a few question marks but I think I got most of the goodies in order.

evanh · 2018-12-08 15:00

If you don't won't any feedback drive then use %00 and leave DIR low.

cgracey · 2018-12-08 15:43

Mode 1101_CDDDDDDDD causes PinA to seek the internal comparator DAC level. With C=1, you can quantize what feedback is required to keep PinA at the DAC level.

cgracey · 2018-12-08 15:55

The !IN negative feedback modes are for driving a pin to the internal DAC level. With C=1, you get to quantize the feedback required to do so.

The IN positive feedback mode %1110_CDDDDDDDD allows non-inverted feedback for using a transistor base or FET gate as the feedback delivery.

jmg · 2018-12-08 19:15

Sounds good.
What is the speed of this mode ?
What is the common mode voltage range ?
A common spec point is to test 100mV overdrive tpd delays.
Vos is not going to be easy to measure - maybe drive to 0 & Vio, and feed a scaled variable supply to find vos.
Eg 1k & 10 ohms is 10mV/V

I think there is no/minimal hysteresis in this mode ?

cgracey · 2018-12-08 22:15

jmg wrote: »

Sounds good.
What is the speed of this mode ?
What is the common mode voltage range ?
A common spec point is to test 100mV overdrive tpd delays.
Vos is not going to be easy to measure - maybe drive to 0 & Vio, and feed a scaled variable supply to find vos.
Eg 1k & 10 ohms is 10mV/V

I think there is no/minimal hysteresis in this mode ?

It goes beyond the rails and has no intended hysteresis.

Comparator mode testing

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