Note: for oscillator selection P2 clocking at 250MHz (for HDMI) cannot be achieved with 12.288MHz, though it can be at 19.2MHz and 26MHz using the following divisor/multiplier ratios if these suit the P2 PLL range...

250 = 19.2/48 * 625
250 = 26/13 * 125, or 26/26 * 250, or 26/52 * 500

Also for HDTV stuff 148.5 MHz happens to be 19.2/64 * 495 and 26 / 52 * 297

Note: for oscillator selection P2 clocking at 250MHz (for HDMI) cannot be achieved with 12.288MHz, though it can be at 19.2MHz and 26MHz using the following divisor/multiplier ratios if these suit the P2 PLL range...

250 = 19.2/48 * 625
250 = 26/13 * 125, or 26/26 * 250, or 26/52 * 500

Also for HDTV stuff 148.5 MHz happens to be 19.2/64 * 495 and 26 / 52 * 297

Maybe using a 12.288 MHz, clipped sine, VCTCXO could even enable calibration under sofware control, both numerically and also thru a filtered pin DAC.

12.288MHz is a rare value, more common are GPS related valued, like 19.2MHz and 26MHz
The PLL means either of those can be used, ans still have whole-number relations with 50Hz/60Hz
19.2M/60 = 320000
19.2M/50 = 384000
26M/50 = 520000
26M/60 = 433333.3333' - so you need a x3 in the PLL, if you want whole-numbers.

I think 19.2MHz or 9.6MHz would be the ideal XO frequency.

The thing about non-even MHz frequencies from TCXO's is that they will require big initial XI (clock input) dividers to get down to something that can be multiplied back up to get to other needed frequencies. When using a big initial XI divider from something around 10-20MHz, very weak VCO pump currents must be used to adjust the VCO, since the divided XI frequency is so low and the correction pulses are infrequency. As that frequency gets multiplied up in the VCO with such gentle feedback current and seldom corrections, the VCO jitter becomes worse at really high final output frequencies. A 10MHz or 20MHz TCXO would ideal, I think.

The thing about non-even MHz frequencies from TCXO's is that they will require big initial XI (clock input) dividers to get down to something that can be multiplied back up to get to other needed frequencies. When using a big initial XI divider from something around 10-20MHz, very weak VCO pump currents must be used to adjust the VCO, since the divided XI frequency is so low and the correction pulses are infrequency. As that frequency gets multiplied up in the VCO with such gentle feedback current and seldom corrections, the VCO jitter becomes worse at really high final output frequencies. A 10MHz or 20MHz TCXO would ideal, I think.

The common / cheap ones are GPS sector and those tend to favour 19.2MHz or26MHz.
26MHz meets your even-MHz request ?
48MHz would be interesting to try.

The thing about non-even MHz frequencies from TCXO's is that they will require big initial XI (clock input) dividers to get down to something that can be multiplied back up to get to other needed frequencies. When using a big initial XI divider from something around 10-20MHz, very weak VCO pump currents must be used to adjust the VCO, since the divided XI frequency is so low and the correction pulses are infrequency. As that frequency gets multiplied up in the VCO with such gentle feedback current and seldom corrections, the VCO jitter becomes worse at really high final output frequencies. A 10MHz or 20MHz TCXO would ideal, I think.

The common / cheap ones are GPS sector and those tend to favour 19.2MHz or26MHz.
26MHz meets your even-MHz request ?
48MHz would be interesting to try.

26MHz would be great!

We've got a 20MHz +-10ppm crystal going on the eval board now.

We've got a 20MHz +-10ppm crystal going on the eval board now.

What's the error of these GPS oscillators, again?

It varies - usually never worse than ±2ppm, and some are ±0.5ppm
The VCTCXOs have a voltage control pin, and are designed to optionally lock to an even better standard, like a GPS derived 1pps, or be calibrated post-reflow.

Shows ±2ppm max for 2 reflows, and ±0.5ppm over -30 to +85°C, with ±.05ppm/°C, 1ppm/ year aging

With the free-DAC's the P2 is well suited to using a VCTCXO

Addit: and some P2 customers will likely use these, in 2019 OCXOs
SiT5711 1 to 60 MHz ±0.005ppm (±5 ppb) or ±0.008ppm (±8 ppb) LVCMOS or Clipped sinewave 3.3V -20 to +70 or -40 to +80 9.0 x 7.0mm
No price or mA on those, but the trend is impressive.
Current listings for OCXO show ±50ppb -40°C ~ 85°C 122mA Surface Mount (9.70 x 7.50 x 4.30mm) for sub $30/100

The thing about non-even MHz frequencies from TCXO's is that they will require big initial XI (clock input) dividers to get down to something that can be multiplied back up to get to other needed frequencies. When using a big initial XI divider from something around 10-20MHz, very weak VCO pump currents must be used to adjust the VCO, since the divided XI frequency is so low and the correction pulses are infrequency. As that frequency gets multiplied up in the VCO with such gentle feedback current and seldom corrections, the VCO jitter becomes worse at really high final output frequencies. A 10MHz or 20MHz TCXO would ideal, I think.

The common / cheap ones are GPS sector and those tend to favour 19.2MHz or26MHz.
26MHz meets your even-MHz request ?
48MHz would be interesting to try.

26MHz would be great!

The last sentence seems not to accord entirely with the first paragraph. 26MHz needs lots of /13 or /26 for integer frequencies, whereas 10MHz needs /5 or /10 or sometimes /1. 9.6MHz has lower divisors than 26MHz for most frequencies and 10MHz for some, e.g. 252MHz is closer to the DVI/HDMI spec than 250MHz and 9.6 * 105/4 = 252.0. I could post more comparisons tomorrow.

Question:
If VCO = n * XI, is a PLL M/D setting of 2n/2 better than n/1?

The thing about non-even MHz frequencies from TCXO's is that they will require big initial XI (clock input) dividers to get down to something that can be multiplied back up to get to other needed frequencies. When using a big initial XI divider from something around 10-20MHz, very weak VCO pump currents must be used to adjust the VCO, since the divided XI frequency is so low and the correction pulses are infrequency. As that frequency gets multiplied up in the VCO with such gentle feedback current and seldom corrections, the VCO jitter becomes worse at really high final output frequencies. A 10MHz or 20MHz TCXO would ideal, I think.

The common / cheap ones are GPS sector and those tend to favour 19.2MHz or26MHz.
26MHz meets your even-MHz request ?
48MHz would be interesting to try.

26MHz would be great!

The last sentence seems not to accord entirely with the first paragraph. 26MHz needs lots of /13 or /26 for integer frequencies, whereas 10MHz needs /5 or /10 or sometimes /1. 9.6MHz has lower divisors than 26MHz for most frequencies and 10MHz for some, e.g. 252MHz is closer to the DVI/HDMI spec than 250MHz and 9.6 * 105/4 = 252.0. I could post more comparisons tomorrow.

Question:
If VCO = n * XI, is a PLL M/D setting of 2n/2 better than n/1?

The lower the XI input divider, the stronger the PLL feedback.

I've been running some Goertzel tests today and i'm getting erratic results.
I am looping the Goertzel output back into itself (via 270R resistor) and taking samples while sweeping from10kHz to 2MHz.
What i'm seeing is quite large phase and power changes as well as a lot of noise.
System clock speed also affects results.
Not sure if I'm doing something wrong (more than likely) .
...
As Goertzel frequency increases power values reduce and phase shifts.
Any ideas?

The Goertzel is measuring a fixed number of NCO cycles. So at higher frequencies, the measurement time is less and the full-scale value is proportionally less.

As for the phase shift, it might be the resistor interacting with the pin capacitance. Or some register delays.

In these plots, the X axis is rows, but there are 2200 columns covering 2MHz, starting at 100k. So the X axis is approximately in kHz.

The response is down 1dB at 2MHz. That's reasonable considering what I have read about the ADC in other threads.

-3dB at 4.9MHz. -6dB at 9.8MHz. It was 9MHz in another test at 160MHz sysclock.

X axis is MHz. Y axis is 20*log10( rho * MHz ), normalized power expressed in dB. Sysclock was 250 MHz. So Nyquist is 125. I scanned to 130MHz, you can see the reflection around 125. The code does 10 measurements at each frequency, creating a vertical line. Then there is a diagonal line between frequencies. I'll eventually modify the code for linear scanning.

I may have been seeing that 5.4MHz peak in the video tests.

I really wish I had the time to improve the ADC front end, to get its bandwidth up to Nyquist, but it's probably beyond the scope of our time frame. It would take some fundamental rethinking.

## Comments

2,768250 = 19.2/48 * 625

250 = 26/13 * 125, or 26/26 * 250, or 26/52 * 500

Also for HDTV stuff 148.5 MHz happens to be 19.2/64 * 495 and 26 / 52 * 297

9,962You can be out by a few percent, even on audio, and no one notices ... until it wobbles.

1,524Reply moved to

http://forums.parallax.com/discussion/comment/1452138/#Comment_1452138

1,524I think 19.2MHz or 9.6MHz would be the ideal XO frequency.

13,07714,494The common / cheap ones are GPS sector and those tend to favour 19.2MHz or26MHz.

26MHz meets your even-MHz request ?

48MHz would be interesting to try.

13,07726MHz would be great!

We've got a 20MHz +-10ppm crystal going on the eval board now.

What's the error of these GPS oscillators, again?

14,494The VCTCXOs have a voltage control pin, and are designed to optionally lock to an even better standard, like a GPS derived 1pps, or be calibrated post-reflow.

This page has a good example of typical specs

Shows ±2ppm max for 2 reflows, and ±0.5ppm over -30 to +85°C, with ±.05ppm/°C, 1ppm/ year aging

With the free-DAC's the P2 is well suited to using a VCTCXO

Addit: and some P2 customers will likely use these, in 2019 OCXOs

SiT5711 1 to 60 MHz ±0.005ppm (±5 ppb) or ±0.008ppm (±8 ppb) LVCMOS or Clipped sinewave 3.3V -20 to +70 or -40 to +80 9.0 x 7.0mm

No price or mA on those, but the trend is impressive.

Current listings for OCXO show ±50ppb -40°C ~ 85°C 122mA Surface Mount (9.70 x 7.50 x 4.30mm) for sub $30/100

1,524The last sentence seems not to accord entirely with the first paragraph. 26MHz needs lots of /13 or /26 for integer frequencies, whereas 10MHz needs /5 or /10 or sometimes /1. 9.6MHz has lower divisors than 26MHz for most frequencies and 10MHz for some, e.g. 252MHz is closer to the DVI/HDMI spec than 250MHz and 9.6 * 105/4 = 252.0. I could post more comparisons tomorrow.

Question:

If VCO = n * XI, is a PLL M/D setting of 2n/2 better than n/1?

13,077The lower the XI input divider, the stronger the PLL feedback.

341As for the phase shift, it might be the resistor interacting with the pin capacitance. Or some register delays.

In these plots, the X axis is rows, but there are 2200 columns covering 2MHz, starting at 100k. So the X axis is approximately in kHz.

The response is down 1dB at 2MHz. That's reasonable considering what I have read about the ADC in other threads.

4,088Is it possible to get a -3db point while you're at it?

341X axis is MHz. Y axis is 20*log10( rho * MHz ), normalized power expressed in dB. Sysclock was 250 MHz. So Nyquist is 125. I scanned to 130MHz, you can see the reflection around 125. The code does 10 measurements at each frequency, creating a vertical line. Then there is a diagonal line between frequencies. I'll eventually modify the code for linear scanning.

I may have been seeing that 5.4MHz peak in the video tests.

13,077I really wish I had the time to improve the ADC front end, to get its bandwidth up to Nyquist, but it's probably beyond the scope of our time frame. It would take some fundamental rethinking.