ADC Noise

189101214

Comments

  • jmg wrote: »
    Tubular wrote: »
    Today I realized we could simply repeat the tests, so immediately after 320 MHz test was done with, drop straight back to 80Mhz and repeat with a now warmed die, and compare trails.


    Can you add a 3rd test point, of Not GIO/VIO - ie the zero current drive resting point (pin not connected).
    Should be nominally half way between, so maybe plot it as (GIO+VIO)/2 vs NC-Pin reading and this should show Zero drifts vs gain drifts.

    In highest gain mode (lowest Rin), you should also be able to measure the mV offset between any two Analog-enabled pins, to gauge the offset voltage from pin to pin.
    A high impedance meter could also measure the DC bias point of an Analog Enabled pin. (deviation from 50% ideal)

    We could have a go at this, jmg.
  • Rayman wrote: »
    Still thinking of changing the pin hardware?
    I think 11 bit ADC is fine...

    Except, if I'm understanding correctly, you have to measure at 16 bits to get those 11 bits. That takes 32x as long as being able to measure at 11 bits. So, every bit of resolution he can add can also be viewed as cutting the sampling time in half. I suspect 8-bit sampling will be a very common bit depth, but it will currently require sampling at 12-13 bits.
  • I don't see why you'd sample for 16 bits if you only need 11...
    Prop Info and Apps: http://www.rayslogic.com/
  • due to noise. If the signals strays by 5 bits, 11 bit precision needs 16 bit resolution. Like: if you want to have a smart leader, you have to vote 32 times for him ;-)
    no reason to reason if you feel feelings: in love with the propeller

    How-2-TACHYON
  • Seairth wrote: »
    Rayman wrote: »
    Still thinking of changing the pin hardware?
    I think 11 bit ADC is fine...

    Except, if I'm understanding correctly, you have to measure at 16 bits to get those 11 bits. That takes 32x as long as being able to measure at 11 bits. So, every bit of resolution he can add can also be viewed as cutting the sampling time in half. I suspect 8-bit sampling will be a very common bit depth, but it will currently require sampling at 12-13 bits.

    Not really, we're just using 16 bits because its easy, pushes things and enables better noise measurement. Its more about gaining understanding, at this point.

  • evanhevanh Posts: 8,097
    edited 2018-11-03 - 19:24:40
    11 bits is about all that is achievable with thermal noise present. And with the castrated sampling of recalibrating for every sample the performance drops so badly that gaining much more depth will only be useful for very slow measurements like temperature probes.

    There is a need to find a far less intrusive calibration method than what Chip has demonstrated.


    PS: If you don't require below 100 Hz response then much greater than 11 bits should be available.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • evanh wrote: »
    11 bits is about all that is achievable with thermal noise present. And with the castrated sampling of recalibrating for every sample the performance drops so badly that gaining much more depth will only be useful for very slow measurements like temperature probes.

    There is a need to find a far less intrusive calibration method than what Chip has demonstrated.

    There are several ways to improve this, its just not priority right now.

    At very least I'd suggest the following sequence GIO - AIO - VIO - AIO - GIO.... means your analog input AIO is being sampled half the time, and can always be calibrated against a neighboring VIO and GIO data point.

    From there, VIO and GIO have a correlation (as you've plotted), and VIO has lower noise than GIO, so its likely these won't ultimately need to be studied at the same resolution as the analog input AIO. We haven't even looked yet at the short term relation between adjacent pin VIO/GIO.

    The question is how to best perform the statistical hobbling, but I would think the autocalibration will end up costing something like 25%, resulting in 90kSps at 11 bit resolution at 250MHz, but still with a flexible choice to trade resolution for speed.



  • I've been reading up a bit on ADC characterization. I think what we need to implement is the least squares sine curve fitting technique as described in IEEE1241 appendix B (probably the 4 term case).

    That will enable us to determine an ENOB figure.

    QR decomposition, anyone?
  • Chip, is the transfer of the ADC driven by analog or is there a clock pulse that drives the transfer synchronously? I ask, because in theory you could stagger 8 pins by a few clock cycles and have 8x the resolution, since they are sampling at different clock intervals. This could be expanded to 32 pins and you'd have 32Mhz sampling capability. If you're running at 256Mhz and have 32Mhz sampling input, that gives you about 8 clocks per sample, or about 4 instructions per sample, to do something.
  • evanhevanh Posts: 8,097
    edited 2018-11-05 - 21:18:17
    Tubular,
    The performance lose due to constant recalibrating is far worse than that. There is substantial downtime to switch back and forth between the sources. But maybe the worst part is the natural continuous flow of a sigma-delta ADC gets disrupted. This introduces aliasing potential where there wasn't any before.

    I want to try and move the thermal tracking portion of the calibration to another pin altogether.


    Pedward,
    Synchronous. This diagram is representative:
    Prop2_ADC_functional.png

    EDIT: The real ADC is more sophisticated, employing current amplifiers. Some hints here - https://forums.parallax.com/discussion/comment/1451855/#Comment_1451855

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • evanhevanh Posts: 8,097
    edited 2018-11-25 - 03:05:22
    And here's the related config bits that aren't in the main document:
    %P..P: low-level pin control (for full function finished die)
    
    	common labelling of pin config bits
    		%C = clocked I/O (extra clock for IN and OUT)
    		%I = invert IN output
    		%O = invert OUT input
    		%HHH/LLL = digital out drive strength
    			000: Fast
    			001: 1k5R
    			010: 15kR
    			011: 150kR
    			100: 1mA
    			101: 100uA
    			110: 10uA
    			111: Float
    		PinA is specified pin number
    		PinB is PinA's odd/even pair
    
    	%0_VVV_CIOHHHLLL = Digital mode (default = %0000000000000)
    		DIR enables PinA digital output
    		%VVV = Digital config
    			000: IN = PinA logic, PinA output from OUT
    			001: IN = PinA logic, PinA output from IN
    			010: IN = PinB logic, PinA output from IN
    			011: IN = PinA schmitt, PinA output from OUT
    			100: IN = PinA schmitt, PinA output from IN
    			101: IN = PinB schmitt, PinA output from IN
    			110: IN = PinA > PinB comparator, PinA output from OUT
    			111: IN = PinA > PinB comparator, PinA output from IN
    
    	%100_VVV_OHHHLLL = ADC_MODE, first order sigma-delta
    		IN has bitstream, sysclock bitrate, for smartpin mode %01111 (Y=0)
    		OUT is PinA digital output, clocked
    		DIR enables PinA digital output
    		%VVV = ADC config
    			000: GIO, 1x (~5 volt range, centred on VIO/2)
    			001: VIO, 1x       "
    			010: PinB, 1x      "
    			011: PinA, 1x      "
    			100: PinA, 3.16x (~1.58 volt range, centred on VIO/2)
    			101: PinA, 10x   (~0.5 volt range, centred on VIO/2)
    			110: PinA, 31.6x (~0.158 volt range, centred on VIO/2)
    			111: PinA, 100x  (~0.05 volt range, centred on VIO/2)
    
    	%101_VV_DDDDDDDD = DAC_MODE (%TT = 00 and %MMMMM = 00000), 8-bit flash
    		OUT enables PinA ADC (config %011), sysclocked bitstream on IN
    		DIR enables PinA DAC output
    		%VV = PinA DAC config
    			00: 990 ohm, 3.3 volt range
    			01: 600 ohm, 2.0 volt range
    			10: 123.75 ohm, 3.3 volt range
    			11: 75 ohm, 2.0 volt range
    		%DDDDDDDD = DAC level
    
    		for %TT = %01 and %MMMMM = %00000, %101_VV_xxxxSSSS = COG_DAC mode
    			%SSSS = Cog/streamer select: sets DAC level (registered?)
    
    		for %00000 < %MMMMM < %00100 = SMART_DAC mode
    			DIR/IN are usual smartpin ctrl
    			%DDDDDDDD ignored, smartpin sets DAC level (registered?)
    
    		for %MMMMM >= %00100 or (%TT = R1x and %MMMMM = %00000) = BIT_DAC mode
    			OUT sets DAC level (clocked?, ADC disabled?, IN = ?)
    				0: 0 = GIO level
    				1: %DDDDDDDD
    
    	%11_VV_CDDDDDDDD = COMP_DAC comparator mode
    		DIR enables PinA digital output
    		%VV = Comparator config
    			00: IN = PinA > D, PinA driven by 1k5R from OUT
    			01: IN = PinA > D, PinA driven by 1k5R from !IN
    			10: IN = PinB > D, PinA driven by 1k5R from IN
    			11: IN = PinB > D, PinA driven by 1k5R from !IN
    		%DDDDDDDD = DAC level for internal analogue compare
    
    
    Updated 20-11-2018 to correct smartpin mode number for capturing ADC bitstream.
    25-11-2018: Reverse the update. Doh!
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • jmgjmg Posts: 14,024
    Tubular wrote: »
    There are several ways to improve this, its just not priority right now.

    At very least I'd suggest the following sequence GIO - AIO - VIO - AIO - GIO.... means your analog input AIO is being sampled half the time, and can always be calibrated against a neighboring VIO and GIO data point.

    Yes, that sounds a good approach for 2 point tracking.
    Similar would be a 3 point calibrate of AIO-GIO-AIO-NC-AIO-VIO, but I think there is no MUX means to make the NC (zero/mid point) measurement ?
    Looks like the 8 choices are all taken, with some signal source ?


    Another useful test could be to shift the Ri, to mostly external by select Gain = 100 and add ~ 533k (low ppm) resistor externally to GIO / VIO and compare that pins drift vs internal node ones.

  • Tubular wrote: »
    I think what we need to implement is the least squares sine curve fitting technique as described in IEEE1241 appendix B (probably the 4 term case).

    It won't help for below 100 Hz while the thermal noise is present.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • jmgjmg Posts: 14,024
    edited 2018-11-03 - 21:46:52
    evanh wrote: »
    I want to try and move the thermal tracking portion of the calibration to another pin altogether.
    That's possible only so far as the pin tracking, which right now is looking partial at best.

    Certainly you could allocate Die temperature reading to a separate pin, but that presumes users have a specific-pin-correction table, which is not looking great across-chips either.

    ie they need to thermally cycle and record the specific P2 device, to create the best correction tables.

    here are some reference numbers I found on the web
    Polysilicon Resistor
    30-100 ohms/square (unshielded)
    100-500 ohms/square (shielded)
    Absolute accuracy = ±30%
    Relative accuracy = 2% (5 µm)
    Temperature coefficient = 500-1000 ppm/°C
    Voltage coefficient ≈ 100ppm/V


    a 50°C change, applied to a (say) 200ppm/°C tracking difference error, is a 1% shift, which is in our 1-2% drifts ballpark.
  • JMG,
    We really don't have the data.


    Tubular,
    I really want to see some temperature-only runs done at fixed 20 MHz. Blowing hot and cold air on the bottom of the board.

    I guess data averages at 1 Hz steps showing stable cold to stable hot. Do a number of pins, maybe them all.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • evanh wrote: »
    Tubular wrote: »
    I think what we need to implement is the least squares sine curve fitting technique as described in IEEE1241 appendix B (probably the 4 term case).

    It won't help for below 100 Hz while the thermal noise is present.

    This is for calculating ENOB
  • evanhevanh Posts: 8,097
    edited 2018-11-03 - 21:46:05
    I'm confident of far more than 11 bits once the thermal noise is dealt with.

    BTW: Sampling rate has a big impact on effective number of bits. Anything we can do to restore uninterrupted sampling is a huge win.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • pedward wrote: »
    Chip, is the transfer of the ADC driven by analog or is there a clock pulse that drives the transfer synchronously? I ask, because in theory you could stagger 8 pins by a few clock cycles and have 8x the resolution, since they are sampling at different clock intervals. This could be expanded to 32 pins and you'd have 32Mhz sampling capability. If you're running at 256Mhz and have 32Mhz sampling input, that gives you about 8 clocks per sample, or about 4 instructions per sample, to do something.

    It's just a simple, synchronous, first-order, delta-sigma converter.
  • ON offers a low-tempco resistor option, but I think we've got plenty of thermal trouble in the FETs, too.
  • Also, all of the resistors are built in common-centroid arrays, so there's a lot of thermal/process cancellation going on. Also, all precision currents are derived from these resistors' ratios.
  • jmgjmg Posts: 14,024
    evanh wrote: »
    I'm confident of far more than 11 bits once the thermal noise is dealt with.

    BTW: Sampling rate has a big impact on effective number of bits. Anything we can do to restore uninterrupted sampling is a huge win.

    I'm not sure what you mean by 'thermal noise' ? - all noise is thermal in nature, but we have here both thermal drift, and low frequency 1/f noise effects.
    Thermal drift will likely affect both Span and Zero - so far we have mainly span tests, and those appear to show a somewhat unexplained tighter error band on VIO and GIO.

    Given the circuit is carefully MID focused, and the resistors are common, that experimental result skew suggests the Temperature coefficient from above, also varies with voltage.
    ie not just ppm/V but also (ppm/°C)/V

    You can extract any number of bits you like, but if the thermal drift is in the order of 1%, many of those bits will have little long-term meaning.
    If the drift varies with actual voltage reading, that makes compensation even harder.
  • evanhevanh Posts: 8,097
    edited 2018-11-03 - 22:35:00
    jmg wrote: »
    I'm not sure what you mean by 'thermal noise' ? - all noise is thermal in nature, but we have here both thermal drift, and low frequency 1/f noise effects.
    The question is, does it affect all nearby pins equally? If so, then one pin's GIO, and maybe VIO, reading can be used to compensate for its neighbours drift. The actual temperature is probably not important, just the relative voltage drift.

    Ie: Using software to do what is often built into the hardware.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • jmgjmg Posts: 14,024
    evanh wrote: »
    jmg wrote: »
    I'm not sure what you mean by 'thermal noise' ? - all noise is thermal in nature, but we have here both thermal drift, and low frequency 1/f noise effects.
    The question is, does it affect all nearby pins equally? If so, then one pin's GIO, and maybe VIO, reading can be used to compensate for its neighbours drift. The actual temperature is probably not important, just the relative voltage drift.
    Ie: Using software to do what is often built into the hardware.
    I'm not optimistic about adjacent pin tracking, as the measured pin to pin and device to device variances are large.
    - part of the problem here is the ADC already uses tracking on the IN/FB paths, and so what is left over is the difference in tracking of two slopes.
    That has more random variance than the original slope, and I think the VIO/GND differences shows a voltage dependence on tracking too, which means how much you correct, needs to consider the voltage applied.

  • It's sure as hell worth investigating.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • I did a test where I started conversions on a 60Hz marker, in order to turn the ambient AC radiation into a standing wave that wouldn't interfere with ADC operation. It didn't seem to do much.

    Here's my code:
    ' 16-bit analog to digital with GIO/VIO calibration
    
    con	p =	5
    
    dat	org
    
    	hubset	##%1_000001_0000011000_1111_10_00	'enable crystal+PLL, stay in 20MHz+ mode
    	waitx	##20_000_000/100			'wait ~10ms for crystal+PLL to stabilize
    	hubset	##%1_000001_0000011000_1111_10_11	'now switch to PLL running at 250MHz
    
    	wrpin	dacmod,#p^1		'output test level on adjacent pin DAC for ADC input
    	wxpin	#1,#p^1
    	wypin	##$8000,#p^1
    	dirh	#p^1
    
    	setse1	#%01<<6+p		'se1 triggers on ADC sample
    
    	getct	time
    '
    '
    ' Sample gio, pin, vio
    '
    loop	addct1	time,##250_000_000/60	'wait for start of ambient AC cycles
    	waitct1
    
    	mov	y,adccyc
    	mov	z,#0
    
    .loop	mov	gio,#0
    	mov	pio,#0
    	mov	vio,#0
    
    	callpa	adcmodg,#getsamp	'get gio sample
    	add	gio,x
    
    	callpa	adcmodp,#getsamp	'get pin sample
    	add	pio,x
    
    	callpa	adcmodv,#getsamp	'get vio sample
    	add	vio,x
    
    	sub	vio,gio			'vio - gio
    	sub	pio,gio			'pio - gio
    	qfrac	pio,vio			'pio<<32 / vio
    	getqx	x
    	shr	x,#8			'get normalized 24-bit sample
    
    	add	z,x
    
    	djnz	y,#.loop
    '
    '
    ' Output result
    '
    	qdiv	z,adccyc
    	getqx	z
    '	shr	z,#8
    	
    	wrpin	dacmod,#30		'output conversion to DAC
    	wxpin	#1,#30
    	wypin	z,#30
    	dirh	#30
    
    	jmp	#loop			'loop
    '
    '
    ' Get sample
    '
    getsamp	wrpin	pa,#p			'set adc/counter mode
    	wypin	#0,#p			'inc on high
    	wxpin	adcpre,#p		'set acclimation period
    	dirh	#p			'enable smart pin, starts acclimation
    	wxpin	adcper,#p		'queue sample period
    	waitse1				'wait for acclimation done
    	akpin	#p			'ack pin
    	waitse1				'wait for sample done
    	rdpin	x,#p			'get sample
    _ret_	dirl	#p			'disable smart pin
    '
    '
    ' Data
    '
    adcmodg	long	%100000_0000000_00_01111_0	'ADC gio
    adcmodp	long	%100010_0000000_00_01111_0	'ADC adjacent pin
    adcmodv	long	%100001_0000000_00_01111_0	'ADC vio
    
    adcpre	long	$20				'ADC acclimation period
    adcper	long	$10000				'ADC sample measurement period
    adccyc	long	$10
    
    dacmod	long	%10110_00000000_01_00010_0	'DAC with random dither
    
    gio	res	1
    pio	res	1
    vio	res	1
    
    x	res	1
    y	res	1
    z	res	1
    
    time	res	1
    
  • Tracy AllenTracy Allen Posts: 6,401
    edited 2018-11-04 - 18:29:50
    cgracey wrote: »
    ON offers a low-tempco resistor option, but I think we've got plenty of thermal trouble in the FETs, too.... Also, all of the resistors are built in common-centroid arrays, so there's a lot of thermal/process cancellation going on. Also, all precision currents are derived from these resistors' ratios.

    I've been lurking and in the dark felt I'd probably missed something about about the structure of the ADC compared with the Prop 1. Thanks Evanh for the representative "Propeller II functional diagram" posted above.

    About the common-centroid business, I'm thinking back to articles by Bob Pease that talked about the thermal design of op-amps (or regulators), and how the differential pairs had to be placed symmetrically in relation to the outputs or thermal sources in general. Un-symmetric time delays in in thermal paths lead to transient offsets, and heat sloshing around leads to excess (1/f) noise.
    Eventually, newer amplifiers took advantage of symmetry and common-centroid layouts (See at "What's All This CommonCentroid Stuff, Anyhow?") <https://www.electronicdesign.com/analog/whats-all-common-centroid-stuff-anyhow> to reject thermal gradients. Most of the CMOS amplifiers we will study, below, do not have any appreciable thermal errors, because the CMOS amplifiers were carefully laid out with good layouts to reject thermal gradients. These were accomplished mostly with the use of symmetry, and not with the use of computers. That is because computers are not generally suitable for analyzing the heat flow among the millions of points inside a silicon die, not to mention the thousands of points in time, when a thermal transient occurs. (from NSC ApNote 1485)

    Here with the smart pin, you have the the high switching frequency generating heat, but more acute may be the input to the four inverters hanging tight to the switching threshold in a kind of class A-B operation, at the point where they have the highest gain and draw the highest quiescent current. In the case of op-amps, the common centroids create symmetry in relation to differential pairs. On Semi must have some technique to simulate and apply the same ideas to the pin arrays, but it shouldn't be a surprise that it has its limits. Although the computer modeling available to On may well be significantly better than it was when Bob wrote that article.

    Are the resistors polysilicon?
  • jmgjmg Posts: 14,024
    cgracey wrote: »
    I did a test where I started conversions on a 60Hz marker, in order to turn the ambient AC radiation into a standing wave that wouldn't interfere with ADC operation. It didn't seem to do much.
    Did you try sampling for a whole mains cycle ?
    Tho if you have triggered on a 1/60Hz-mains locked timer, you should be capturing the same smaller slice of 60Hz effect each time, so you may gain little. Just more samples, instead of some-wait-some-wait.. ?

  • jmg wrote: »
    cgracey wrote: »
    I did a test where I started conversions on a 60Hz marker, in order to turn the ambient AC radiation into a standing wave that wouldn't interfere with ADC operation. It didn't seem to do much.
    Did you try sampling for a whole mains cycle ?
    Tho if you have triggered on a 1/60Hz-mains locked timer, you should be capturing the same smaller slice of 60Hz effect each time, so you may gain little. Just more samples, instead of some-wait-some-wait.. ?

    I tried whole cycles as well as constant offsets. Not much improvement.
  • Tracy, the resistors are 1kohm/sq P-plus polysilicon.
  • Tubular,
    Data from a group of eight pins should be enough - P0 to P7. Don't worry about the temperature probe, although it would be nice to know the general range.

    Regular min, max, and average of raw ADC readings from GIO only (use continuous running ADC) with room temp air blowing on the underside of the P2D2 board while at 20 MHz. Continue recording while using heated air to produce a rising temperature. Stop when it levels out.

    I'm not sure about suitable record interval: 10 Hz might be more useful than 1 Hz.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
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