Earlier I discussed my 65ISR design. Pretty quickly the major flaw was found, which is high interrupt-latency. I was already aware of that flaw.
I'm not very serious about the 65ISR as it is mostly an exercise in designing a super-tiny processor --- this is an uninteresting subject from the programmers' perspective --- writing programs in such a restricted environment (two 8-bit registers) is challenging, but not fun (somewhat like building a ship in a bottle).
I'm more serious about my TOYF design. This is a pretty powerful processor that should be competitive in the real-world for both price and performance (the 16-bit corner of the real-world, which is getting smaller every year as most people are upgrading to the 32-bit ARM Cortex).
The TOYF is pretty powerful, but it lacks interrupts, so you have to use a paced-loop. This can also be challenging and unfun. If you make your heartbeat fast enough that you don't lose any I/O data, you have to break up your bigger tasks into tiny pieces and do the pieces one per iteration.
There is a similarity here with the 65ISR in which the main-program needs to be punctuated by BRK instructions.
The TOYF is mostly for motion-control in which a paced-loop is typical anyway.
The TOYF is a VLIW processor loosely based on the MiniForth that I wrote the development system for when I was employed at Testra.
The TOYF only has 3 instructions per opcode, whereas the MiniForth had 5 --- but the TOYF can do addition in one instruction, which the MiniForth couldn't.