ADC Noise

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  • Another test would be to run 3 ADCs - one GND ,one VCC ,one cap decoupled (2 caps vccc.gnd?
    ) and plot all 3, checking for correlation.

    How far -ve (below gnd) can an adc channel measure?
  • Can anything be causing some phasing that would produce a low frequency “beat” frequency modulation. Beat frequency being the difference between two similar frequencies.
  • I was looking at some low frequency noise once are realized it was coming from the florescent lamp in my magnifier...
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  • ha, thats a classic...
  • I'm here with OzPropDev and we're able to duplicate what Chip and Peter were seeing on the CRO

    Peter's P2D2 has two 3v3 regulators and the top one near the P2D2 sign has a much quieter output. This seems to supply the high pins ?P56~63? though we're not 100% sure of this. So we changed the analog pin being studied up to 56 and 59, but these seem just the same.

    Using the can of freeze spray causes the dac output to shift significantly - see attached screenshot. Its not clear what that means, though. Note we have added a shr i, #2 to scale a bit differently (looking at bits 2..9 rather than 0..7.

    In the attached scan we've slowed down the horizontal to 1sec/div, and the cro wraps around and over-writes. The freeze spray was applied at about 85% of the horizontal time scale, resulting in that sudden drop, then the waveform wraps around and starts recovering gradually as things warm up again, up to the 60% of horizontal mark

    Thats about as far as we've got, so far.
    800 x 480 - 39K
  • Tubular wrote: »
    Using the can of freeze spray causes the dac output to shift significantly - see attached screenshot. Its not clear what that means, though. Note we have added a shr i, #2 to scale a bit differently (looking at bits 2..9 rather than 0..7.
    Interesting.
    Without the scaling, 0.85 divn I make to be ~10bit precision level.
    With scaling, that's then ~8b level.
    ie the Freeze dT is moving ADC a little over 1 LSB.8bit but in a smooth manner.

    Does that very much with SysCLK changes ?

    With a multitrace scope, you could run multiple channels, and capture Cal=GND, Cal=Vio and Some measure voltage, 50% Vio
    Maybe a calibrate pass can do some temperature tracking ?
  • I know there are limitations to the design that have to do with matching qualities, plus ratios of intended C and R to parasitics. The whole thing is the size of a sharp pin head.
  • Has anyone fully enclosed it with a grounded rf shield yet?
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  • Yeah i think we should look at adjacent channels in the same group. Good idea jmg
  • cgracey wrote: »
    I know there are limitations to the design that have to do with matching qualities, plus ratios of intended C and R to parasitics. The whole thing is the size of a sharp pin head.

    The good news is with the P2 smart pin resource, you can create a PWM DAC for 14/15/16 bit region precise sweeps, and then capture expected : measured error histograms for the ADC, & DAC, in a self-test example you can publish.

    A triangle sweep is useful in such tests, as that gives 2 data points per step, but separated in direction and time.

    To get best DAC checking, maybe 2 channels, that 'swap over' from (PWM -> filter-> ADC) and (DAC-> ADC), then the PWM calibrates the ADC, and then uses that to measure DAC points, to try to reduce ADC errors in DAC checking.

    If the DAC is measuring much better than ADC, then maybe a Difference/instrumentation amp like INA826 could be used to amplify PWM(filter)-DAC) ?
  • Here's the capture looking at 4 adjacent pins simultaneously,
    p52 yellow
    p53 cyan
    p54 magenta
    p55 dark blue

    we took out the scaling so are now looking at 8 LSB's (7..0) again.

    the cyan is wrapping (underflowing). I moved the baselines down to the bottom of the screen, 1 div lower than previous post.

    The Yellow, Magenta, Cyan channels seem vaguely similar. The dark blue seems to dip a bit less, and also maybe takes longer to recover.
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  • cgraceycgracey Posts: 9,553
    edited October 12 Vote Up0Vote Down
    Tubular wrote: »
    Here's the capture looking at 4 adjacent pins simultaneously,
    p52 yellow
    p53 cyan
    p54 magenta
    p55 dark blue

    we took out the scaling so are now looking at 8 LSB's (7..0) again.

    the cyan is wrapping (underflowing). I moved the baselines down to the bottom of the screen, 1 div lower than previous post.

    The Yellow, Magenta, Cyan channels seem vaguely similar. The dark blue seems to dip a bit less, and also maybe takes longer to recover.

    Great idea to look at the noise patterns concurrently of neighboring ADCs! That should reveal if the noise cause is systemic or related to the individual ADCs. If the latter is the case, only design improvement can help. I will run a similar test.
  • jmgjmg Posts: 12,069
    edited October 12 Vote Up0Vote Down
    Tubular wrote: »
    Here's the capture looking at 4 adjacent pins simultaneously,

    What is the analog driving test condition for these tests ?

    The temperature skews at least all move in the same direction :)

    Notice the noise is not much correlated, so that tends to eliminate power supply common effects.
    Tubular wrote: »
    we took out the scaling so are now looking at 8 LSB's (7..0) again.
    Checking that's lower 8b of a 16b full scale ?
    That makes a full 3v3 span equiv to 0.39%, but we can't be certain those are all the same upper bits ?
    Maybe do a scaling pass, to check the Ch-Ch matching here. eg >> 3 would be 3.125% full screen error band.

  • The upper bits are what they are, it'll wrap around/underflow.

    Not sure what you mean by scaling pass, jmg?
  • Sorry yes its the lowest 8 bits again. 0.39% = 6.6 vertical divs on the CRO.
  • what is being used to generate the original analog signal? And what should it look like?
  • Tubular wrote: »
    The upper bits are what they are, it'll wrap around/underflow.

    Not sure what you mean by scaling pass, jmg?

    I was just meaning reduce the scale somewhat, so you can be sure all channels are on the same page.
    With the high zoom, and wrap, channels that are 0.39% apart, will appear to be identical on your zoomed plot.

    I'm not sure what Gain/Offset matching Chip expects, but as these ADCs are all independent, there will be more variation than a classic MCU with a single multiplexed ADC.
  • Seairth wrote: »
    what is being used to generate the original analog signal? And what should it look like?

    The plots on this page are just thermal-shock ones.
    Static Analog In, so the 'ideal' plot is a single, clean, horizontal line ;)
  • Chip, what does the ADC point at? One of the rails? Can we try outputting from a DAC on the same pin to set something midrange?
  • OK, so the ADC was actually pointing at Ground, in previous testing.

    We swapped over to looking at the VIO (local 3v3) rail. At first glance, VIO has a similar amount of noise, but has a reduced dip when hit with the freeze spray. The polarity of the dip is the same as the ground dip - negative going when cooled

    Then we switched across to adc mode (%100011) and connected to 2 x AA battery cells via 100 ohms (ie a real measurement). Performance was similar to the Vio (3v3) case both in noise and dip when cooled.
  • Tubular wrote: »
    OK, so the ADC was actually pointing at Ground, in previous testing.

    We swapped over to looking at the VIO (local 3v3) rail. At first glance, VIO has a similar amount of noise, but has a reduced dip when hit with the freeze spray. The polarity of the dip is the same as the ground dip - negative going when cooled

    Then we switched across to adc mode (%100011) and connected to 2 x AA battery cells via 100 ohms (ie a real measurement). Performance was similar to the Vio (3v3) case both in noise and dip when cooled.

    Sounding hopeful - do you think the thermal dip is (appx) linear, across the range, allowing a GND / VIO calibrate to (mostly) compensate for thermal effects, if done at the same time as the ADC reading ?
  • We also did a test attempting to self-heat the region nearest the ADC pin being observed.

    For this we were watching ADC on pin 50, but we had pins 49 and 51 each driving about 33 mA load. If these fets each have a 19 ohm resistance, thats about 80 mWatts of heating in the region. However we didn't observe any meaningful effects (no discernable rise) on the ADC LSBs value.
  • jmgjmg Posts: 12,069
    edited October 12 Vote Up0Vote Down
    Whilst you are on ADC & Pin, I think these modes are valid Up/downs that might have useful temperature slopes (due to resistance & mosfets ). for die temp sense ?

    100011_0_001_100   'ADC PinA, 1k5 Up,   1mA Down   (nom 3v3-1.5V)
    100011_0_010_101   'ADC PinA, 15k Up,   100uA Down (nom 3v3-1.5V)
    100011_0_011_110   'ADC PinA, 150k Up,  10uA Down  (nom 3v3-1.5V)
    100011_0_100_001   'ADC PinA, 1mA Up,   1k5 Down   (nom 1.5V)
    100011_0_101_010   'ADC PinA, 100uA Up, 15k Down   (nom 1.5V)
    100011_0_110_011   'ADC PinA, 10uA Up,  150k Down  (nom 1.5V)
    

    useful here would be 4 chans as before, but with Ch1 = GND, Ch2 = Vio, Ch3 = Current Source/R sink, Ch4 = Current sink/ R Source & same Thermal-hit plot.
    Usually I think higher resistors have worse temperature coefficients.
  • jmg, I couldn't get those other components to pull in, at first glance, but was mostly testing 000 = strong and 111=float conditions. I did try a couple of resistive combinations but the pin output seemed set on 1.65V. This is possibly how its meant to be, i need to study the docs more. I also will try current sources

    I noticed when switching to ADC measurements from Bpin (100010 mode) the noise seemed standard despite no connection. Normally no connection results in lots of noise, as it should, certainly this is the case measuring the A pin.

    We also noticed in the "magnified" ADC modes, 100100, 100101, 100110, 100111 the noise we're used to was replaced with a solid low or high on those LSBs - ie it looked like code 00000000 or 11111111 was being sent to the DAC. Again, that might be correct.

    Thats all I can do on it for today

  • Tubular, thanks for doing all those experiments.
  • Tubular wrote: »
    jmg, I couldn't get those other components to pull in, at first glance, but was mostly testing 000 = strong and 111=float conditions. I did try a couple of resistive combinations but the pin output seemed set on 1.65V. This is possibly how its meant to be, i need to study the docs more. I also will try current sources
    thanks, maybe something else is needed, to enable the Resistor & Current & ADC all at the same time on one pin ?
    1.65V is where I'd expect the pin to settle, with ADC in, no output drive and no external pin drive.

  • cgraceycgracey Posts: 9,553
    edited October 12 Vote Up0Vote Down
    I checked conversion noise from two adjacent pins to see if there was any apparent correlation. I don't see any. It seems that each ADC has a life of its own.

    In the picture below, you are seeing the lower 8 bits of two 16-bit conversions of steady signals output to 3.3V DACs. The top and bottom traces are are the data, while the middle trace is their difference. On the vertical axis, each graticule spans ~15.5 conversion steps, or ~780uV. You can see that the ADC measurements meander around:

    ADC_noise_diff.jpg

    I don't know how to improve this performance. I suspect an improvement can only come through better design in the future. For now, this is what we've got.

    I want to hook up a microphone on an ADC pin and play the data out a DAC pin. That would tell a lot, really quickly. The ear is a great spectrum analyzer.

    Here is the program I used to generate the traces:
    ' 16-bit analog to digital noise check
    
    con	p =	4
    
    dat	org
    
    	hubset	##%1_000001_0000011000_1111_10_00	'enable crystal+PLL, stay in 20MHz+ mode
    	waitx	##20_000_000/100			'wait ~10ms for crystal+PLL to stabilize
    	hubset	##%1_000001_0000011000_1111_10_11	'now switch to PLL running at 250MHz
    
    	wrpin	adcmod,#p+0			'adc on
    	wxpin	adccnt,#p+0
    	wypin	#0,#p+0
    
    	wrpin	adcmod,#p+1			'adc on
    	wxpin	adccnt,#p+1
    	wypin	#0,#p+1
    
    	or	dira,#%11<<p			'enable counters
    
    
    	setse1	#%01<<6+p			'se1 triggers on adc sample
    
    loop	waitse1					'wait adc samples
    
    	rdpin	n0,#p+0				'get adc samples
    	rdpin	n1,#p+1
    
    	add	n0,#40				'make any adjustments needed to keep signals centered
    	add	n1,#0
    
    	setbyte	dacmod,n0,#1			'output lower byte of sample 0 to P30 DAC
    	wrpin	dacmod,#30
    	dirh	#30
    
    	setbyte	dacmod,n1,#1			'output lower byte of sample 1 to P31 DAC
    	wrpin	dacmod,#31
    	dirh	#31
    
    	jmp	#loop				'loop
    
    
    i	long	32
    
    n0	long	0
    n1	long	1
    
    dacmod	long	%10110_00000000_00_00000_0
    
    adcmod	long	%100001_0000000_00_01111_0
    adccnt	long	$FFFF
    
    1290 x 1009 - 275K
  • TubularTubular Posts: 3,128
    edited October 12 Vote Up0Vote Down
    if you get a chance Chip, have a look at the 'zoomed in' modes such as 3x, 10x, 100x. They seemed to behave differently

  • cgraceycgracey Posts: 9,553
    edited October 12 Vote Up0Vote Down
    Tubular wrote: »
    if you get a chance Chip, have a look at the 'zoomed in' modes such as 3x, 10x, 100x. They seemed to behave differently

    Will do. I'm finding the ADCs work below 1MHz. I figured they'd saturate with such a long clock period, but they seem to work down to ~150KHz. I wouldn't recommend operating them below 1MHz, or maybe even 5MHz. They have no top speed limit, apparently.

    I'm wondering if that ~1.6mV of measured noise that never goes away might just be caused by VIO switching in the I/O pad. The only fast-moving parts in the ADC are the flipflop and the current switches that are driven by its Q output. I think those things banging around at other than 50% duty cycle create irregular patterns on VIO which form a bit of a positive-feedback noise generator that makes things worse. I should have put some 3.3V bypass caps in the I/O pad. That might have dampened things so that the noise floor would be way less than 1.6mV.

    I'm wondering if the magnification modes, which handily self-bias the pin, are better behaved because they can get closer to 50% duty cycle, open loop, and not suffer regenerative noise patterns. I will check...
  • cgraceycgracey Posts: 9,553
    edited October 12 Vote Up0Vote Down
    Tubular, I'm not seeing any notable difference between the zoom modes and the others.
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