P2D2 - An open hardware reference design for the P2 CPU

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  • Late to this thread, but I have a few suggestions, based on our experience yesterday. Maybe this is just a checklist for what Parallax needs:

    1) Make a good 3mm, or even 5mm center hole under the chip.
    2) This really needs a RESn pushbutton to ground, along with a RESn pullup.
    3) Make it twice as big, or 4x, even. Get some distance between parts and use way stronger voltage regulators.
    4) Go four layers and have a dedicated internal or bottom ground plane for heat dissipation.
    5) Put a power connector and power switch on for proper power cycling and startup.
    6) Add a 1.6V brownout detector that pulls RESn low.
    7) Put some jumpers in for opening up VDD and VIO(s).
    8) Centralize 3.3V VIO generation and have C-L-C filters on sets of 4 or 8 pins with a jumper on each supply side.
    9) A nice GND post would be good.
  • RaymanRayman Posts: 9,716
    edited 2018-09-28 - 23:35:19
    Why 4 layer? I don't think it will help with heat...

    Seems simple enough that 2 layers is fine to me...

    Ok, I might be wrong about that. I think it may be the total amount of copper that matters.
    If 4 layers means more copper, that's better.

    But maybe 2 layers with extra thick copper is just as good?
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  • P2D2 is kind of a chip in a module rather than a development board but it is designed to be plugged into matrix board or a dev board very easily or just as easily run stand-alone.
    My pic chip is also my brownout detector btw.
    I love ground posts but this is a tight module, let me look at whipping up a quick dev board for it to plug into which will have all those buttons and things.

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  • jmgjmg Posts: 13,918
    I do appreciate the helpful info on parts but don't think I ever need to use them.
    That info is also partly for Chip who was talking about SMPS boards.
    Are you going to be evaluating any hardware at all?
    Of course, but my P2 software skills are way below others, so I'll not hurry getting HW.... It will be more use on someone else's desk.

  • jmg wrote: »
    I do appreciate the helpful info on parts but don't think I ever need to use them.
    That info is also partly for Chip who was talking about SMPS boards.
    Are you going to be evaluating any hardware at all?
    Of course, but my P2 software skills are way below others, so I'll not hurry getting HW.... It will be more use on someone else's desk.

    But you'll miss out on all the fun plus we can get to make requests and critique your work too! :)



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  • jmgjmg Posts: 13,918
    edited 2018-09-29 - 01:23:40
    cgracey wrote: »
    Late to this thread, but I have a few suggestions, based on our experience yesterday. Maybe this is just a checklist for what Parallax needs:

    1) Make a good 3mm, or even 5mm center hole under the chip.
    2) This really needs a RESn pushbutton to ground, along with a RESn pullup.
    3) Make it twice as big, or 4x, even. Get some distance between parts and use way stronger voltage regulators.
    4) Go four layers and have a dedicated internal or bottom ground plane for heat dissipation.
    5) Put a power connector and power switch on for proper power cycling and startup.
    6) Add a 1.6V brownout detector that pulls RESn low.
    7) Put some jumpers in for opening up VDD and VIO(s).
    8 ) Centralize 3.3V VIO generation and have C-L-C filters on sets of 4 or 8 pins with a jumper on each supply side.
    9) A nice GND post would be good.

    Hmm... those are quite large changes to the P2D2 approach.

    If you are doing a broader use board, I would include

    10) USB interface (this also solves most of 5), the decision is which USB bridge to use - cheapest, or fastest ?


    4x larger and 4Layers is quite a bump in board price, and smaller boards are more appealing to most users (see FLiP)

    - I'm suggesting the next P2D2 are run in 2oz or 3oz, as that's an easy change, it may be 4L is not needed.

    See my earlier & edited post around Regulators.
    I favour the PGood ones, so they include the 6)
    The price curve is such that more amps does not cost much more, and 'modern' is better specs than 'older'.

    Short list Switching choices seem to be

    Mature: NCP3170A/B SO-8 from OnSemi 4.5~18V 3A PGood, 38c/2.5k 90 mΩ High-Side, 25 mΩ Low-Side Switch (typ at 12 V)
    Newer: AOZ2261QI-15 2.7V~28V 8A PGood, 54c/1k 49c/3k 22-QFN (4x4) 26 mΩ / 12 mΩ typ at 12V

    and for Linear (3v3) I like the Price/power of SOT223, eg this modern LDO, low IQ version of the '1117'
    LDL1117S33R STMicroelectronics IC REG LINEAR 3.3V 1.2A SOT223 2500 $0.1234

  • Peter JakackiPeter Jakacki Posts: 8,641
    edited 2018-09-29 - 01:21:36
    I'm laying out a dev board for the P2D2 to plug into with USB serial as well as USB and switches and VGA, audio, plus proto area etc. It may even include a fan which is practical for dev board usage if we need to push the board.

    I don't think though that 6/6 rules and heavy copper is easy or cheap though. The P2D2 can be exactly what it is, a module to facilitate designs and also a reference design to copy and adapt from.

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  • Something that might be useful is a temperature sensor. This could help developers know if they're running the chip too hot, and whether a heat sink is required for their application.
  • The pic chip is the brownout, the temperature sensor, the reset on break, the reset pulse shaper etc. Imagine if I needed to use discretes!

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  • Excellent!
  • jmgjmg Posts: 13,918
    I don't think though that 6/6 rules and heavy copper is easy or cheap though.
    Maybe, but the P2D2 is closer to 9/9 or 10/9 rules, with a 0.5mm lead pitch main device, than 6/6 rules.


  • jmgjmg Posts: 13,918
    I'm laying out a dev board for the P2D2 to plug into with USB serial as well as USB and switches and VGA, audio, plus proto area etc...

    Someone else mentioned WiFi...
    Have you thought about adding WiFi module footprint to the plug-in board ?

    I notice the UNO WIFI Rev2 is showing at Mouser, eta 6 Nov, for $44.90 - been pending a while.

  • Given the analog sensing on this Chip and all its smartpins, its pretty likely we'll be able to measure chip temperature on-chip
  • jmgjmg Posts: 13,918
    Tubular wrote: »
    Given the analog sensing on this Chip and all its smartpins, its pretty likely we'll be able to measure chip temperature on-chip

    Interesting idea - I wonder what typical errors that will have ?
    There was a table somewhere of the smart pin modes ?, but it may be possible to drive a current setting into a NMOS=on output, and read the VOL, and from that derive the temperature of that bonding pad area ?
  • We should have 4 layers just to improve the performance of the analog capabilities. Makes no Sense to look for the last cent
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  • ErNa wrote: »
    We should have 4 layers just to improve the performance of the analog capabilities. Makes no Sense to look for the last cent

    And 4 layers allows you a contiguous, uninterrupted heat dissipation plane.
  • I can't see myself ever pushing a P2 that hard that it overheats since I've never needed to push a P1 that hard that it even gets warm. But for this exercise while I am doing up a dev board I will add extra layers to the P2D2 and get them manufactured both in 2 and 4 layer versions, just for comparison. But while it is a no-brainer to have a ground layer, what do we really need for the supply rails? Should I split up the plane for 1.8V and 3.3V? I would leave the top and bottom layers as they are now and put the extra ground layer just under the top layer.

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  • When it comes to the power supply, we need very short connections from 1.8 and 3.3 to ground. Thats done by mlcc (multi layer ceramic capacitors). The component side (Prop) is layer 1, ground plain layer two. Then the vias to the ground layer can be uses as solder pads for the mlcc. So we have very low inductance between ground and V, that is, current spikes from the chip can pass through the mlcc's. On the other side, the voltages have to show low noise. analog.com/en/technical-articles/reduce-emi-and-improve-efficiency-with-silent-switcher-designs.html gives a good introduction. The inductance of the current path from the switcher to the load should have a positive effect, like a pi-filter. And analog voltages should be separated from digital ones.
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  • jmgjmg Posts: 13,918
    ErNa wrote: »
    When it comes to the power supply, we need very short connections from 1.8 and 3.3 to ground. Thats done by mlcc (multi layer ceramic capacitors). The component side (Prop) is layer 1, ground plain layer two. Then the vias to the ground layer can be uses as solder pads for the mlcc. So we have very low inductance between ground and V, that is, current spikes from the chip can pass through the mlcc's. On the other side, the voltages have to show low noise. analog.com/en/technical-articles/reduce-emi-and-improve-efficiency-with-silent-switcher-designs.html gives a good introduction. The inductance of the current path from the switcher to the load should have a positive effect, like a pi-filter. And analog voltages should be separated from digital ones.

    If you strive for the shortest paths, then the mlcc caps need to go on the rear side of the board.

    ...But for this exercise while I am doing up a dev board I will add extra layers to the P2D2 and get them manufactured both in 2 and 4 layer versions, just for comparison. But while it is a no-brainer to have a ground layer, what do we really need for the supply rails? Should I split up the plane for 1.8V and 3.3V? I would leave the top and bottom layers as they are now and put the extra ground layer just under the top layer.
    Given the skew in current drains Chip has reported, it would look like 1.8V needs to 'get the most copper', plus Chip's post above suggests he wants to split the 3v3 up more, with more filtering ?
    Moving some of the caps to the rear side could allow more room for 3v3 options.

  • jmgjmg Posts: 13,918
    cgracey wrote: »
    ErNa wrote: »
    We should have 4 layers just to improve the performance of the analog capabilities. Makes no Sense to look for the last cent

    And 4 layers allows you a contiguous, uninterrupted heat dissipation plane.

    pcbway appears to allow 1oz or 1.5oz on inner layers, with no price change.

    I find this on another PCB web site
    Max Outer Layer Copper Weight (Finished)	15oz
    Max Inner Layer Copper Weight	12oz
    Min Tracing/Spacing	For External layers: 
    4oz Cu 9mil/9mil 
    5oz Cu 11mil/11mil 
    6oz Cu 13mil/13mil 
    12oz Cu 20mil/32mil 
    15oz Cu 32mil/40mil 
    
    For Internal layers: 
    4oz Cu 8mil/12mil 
    5oz Cu 10mil/14mil 
    6oz Cu 12mil/16mil 
    12oz Cu 20mil/32mil 
    
    With 0.5mm pin pitch, 11 mil pads, it looks like up to 4 oz is viable on outer layers, and maybe just ok on inner layers too.

    Using a quick base pcbway quote form, 100pcs, 6/6 rules cost no more than 8/8 or higher, and 0.3mm hole is the smallest before prices climb, but 0.3mm should be fine for P2D2

    2L base is $47 $61 with 2oz ticked, $234 with 3 oz ticked, $470 with 4oz

    4L base is $111, $112 with 1.5oz inners, $130 with 2oz ticked (not clear if that means all 4 layers ?) $1075 (!) with 3oz ticked, $1172 for 4 oz (that hike suggests all layers?)
    4L,2oz, 300 pcs is $227, 1000pcs is $560, so that's 56c/board

    Looks like 2oz is a small adder, but 3,4 oz have steep price ramp, & even more on 4L (notice here if you need 2L 4oz, you are better to flip to 4L 2oz, if that is practical )

    To me that makes 4 layer, 2 oz look like the sweet spot.

    For fun, I ticked Aluminium board, for those P2-over-clockers out there ;)

    metal core in middle, 2L = $377, same price for 1,2,3,4 oz (2L 4oz Al inner, is cheaper than 2L 4oz ?)
    metal base on bottom is $389. Seems to not allow Aluminium board and 4L
    The metal on bottom could allow great heatsink transfer, but bumps decoupling to the top side.
    300 pcs is $501, so there is a setup cost for Aluminium board
  • Given the analog sensing on this Chip and all its smartpins, its pretty likely we'll be able to measure chip temperature on-chip

    My thought too. Figure some standard thing.
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  • I've sent a lot of orders through pcbway, never noticed that 1.5oz inner option, thanks for pointing out

    Be careful when you select 2oz, the track/space changes to 8 mil, and if you want combined with 6 mil track/space it gets expensive.

    But to be honest that 1.5oz inner would do whats needed
  • in the end, a heat sink can not work better than the heat transfer at the boundery allows. If the pcb is pure copper and thermally isolated, it will heat up to any temperature after some time. So the trick is to conduct the heat from the chip to a large surface with a little temperature drop and at the surface remove the heat, e.g. by radiation or air or water or another heat conductor. But I really think, we are not limited by the temperature limit now and in the next time. IF we find a killer app, no question there will be a hardware revision. And, most important, the child is fletched (?) and will fly alone.
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  • jmgjmg Posts: 13,918
    Tubular wrote: »
    I've sent a lot of orders through pcbway, never noticed that 1.5oz inner option, thanks for pointing out

    Be careful when you select 2oz, the track/space changes to 8 mil, and if you want combined with 6 mil track/space it gets expensive.
    Makes sense, given the table above.

    For this board, 8/8 rules are fine, as it has 11 mil pads, on 0.5mm pitch.

  • jmgjmg Posts: 13,918
    I can't see myself ever pushing a P2 that hard that it overheats since I've never needed to push a P1 that hard that it even gets warm. But for this exercise while I am doing up a dev board I will add extra layers to the P2D2 and get them manufactured both in 2 and 4 layer versions, just for comparison. But while it is a no-brainer to have a ground layer, what do we really need for the supply rails? Should I split up the plane for 1.8V and 3.3V? I would leave the top and bottom layers as they are now and put the extra ground layer just under the top layer.

    What versions of PADS ASCII can your version of Protel import ?
    PADS seems to import the native Protel 99 files fine, just had to nudge the pour priority and that was all. ( & I cleaned up the rules, so all nets are the same, and applied w10/c8 to the PCB)
  • Peter JakackiPeter Jakacki Posts: 8,641
    edited 2018-09-30 - 02:59:03
    I'm not sure if Chip was using the 1.8V regulator on the pcb as he seemed to be using the PSU over long leads for this purpose even though there is a track between two vias that can be cut to measure 1.8V current. When I make up my board I will measure the noise and current myself and report back the results (including 1.8V high-frequency current).

    I know some will quote from text books (the P2 is not a text book design btw) but this design is tight and I visualize current/switching paths as I lay out pcbs so I can't see why we should have any real problems in a practical way. Remember that this pcb is small and the regs are very close to the P2. Anyone who wants to improve upon this reference design can do so, the files are in the Dropbox. Then you can send off the artwork to get pcbs made, find out how much they end up costing, how hard or easy they are to assemble, and how well they work, then report back, just as I did.

    The other thing, since I purposely designed the pcb to have components on one side only (other than the reversed microSD option) so that it can be mounted to a heatsink or a metal case directly. As has been mentioned, you can have more layers, but in the end they need to dissipate heat too, so you will need air flow over a large surface such as the outside of a metal case or heatsink.

    edit: From the 1.8V reg filter cap to the chip is very short and not too close either as the switching reg will generate ground noise. The bright yellow is the copper on the top side with the dark yellow a mid-layer that I've added as an option (rough at the moment) along with vias from each pin to that layer. I don't intend to have any components on the reverse side for the P2D2 design itself for various reasons. So this pcb can be made with 2 layers or 4 layers but except for extreme testing I really don't think we will need 4 layers. The ground plane mid layer might be useful for spreading the heat a little better with standard copper but in the end it will need to be dissipated properly.

    p2d2-1v8.png

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  • jmgjmg Posts: 13,918
    edit: From the 1.8V reg filter cap to the chip is very short and not too close either as the switching reg will generate ground noise. The bright yellow is the copper on the top side with the dark yellow a mid-layer that I've added as an option (rough at the moment) along with vias from each pin to that layer. I don't intend to have any components on the reverse side for the P2D2 design itself for various reasons. So this pcb can be made with 2 layers or 4 layers but except for extreme testing I really don't think we will need 4 layers. The ground plane mid layer might be useful for spreading the heat a little better with standard copper but in the end it will need to be dissipated properly.
    For 2L designs, I found the 3v3 vias can be moved closer to the PADS, which gives more copper left for the 1v8.
    I also extended the 1v8 copper pour under the xtals, for 2L use, so the voltage drop from the regulator blocks is less.
    Chip mentioned 200mV of cable drop, which suggests users should really not be using bench supplies, as that will put 2.0V into the core, when it idles, in order to give 1.8V at full power.

    I also found the Q1 reset TRX that was lost in the PIC addition, can fit under the board, allowing a dual purpose use. It can use J1 as the base-CAP, in that case.

    Which versions of PADS ASCII can you read ? Not sure if I can export 'old enough' for Protel 99 ?
  • Peter what if we flipped your module upside down during use? You already have the microsd footprint on the reverse side. You might just need to add a reset button footprint.

    The big ground pour would then be uppermost for efficient heat rising up and getting away.

    You then have heaps of space for pin labels with big easy-to-read labels.

    While Chip was suggesting a ground post, perhaps a hole (or holes) like the microbit has, near one edge of the board, could make easy ground connection easy.

    Just some thoughts, grand total 2c.
  • @jmg - you have your own kitchen, just cook up your "improvements" and serve it up as I have done.

    If I put it closer then someone will say "it can go closer". If I make the tracks thicker, someone will say "they can be thicker". If I add more layers I'm sure someone will say "add more layers". What I am also sure of is that someone will always say something, but not everyone will do something.

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  • jmgjmg Posts: 13,918
    @jmg - you have your own kitchen, just cook up your "improvements" and serve it up as I have done.

    Err, yes, that's exactly what I am attempting to do - if you tell me what versions PADS files you can read, I can export that and send you the "improvements" all done...
    Import into KiCad seemed to work quite well, and import into PADS also went smoothly.
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