P2 ADC sampling speed projection?

Perhaps I missed it but is there an estimated ksps for the smartpin ADC function?

Mike R...
The difference between theory and practice is that, in theory, there is no difference between theory and practice, but in practice, there is.

Comments

  • jmgjmg Posts: 13,520
    The DOCs just say "Delta-sigma ADC with 5 ranges, 2 sources, and VIO/GIO calibration"
    - so that means a fairly modest sampling rate. The linearity and noise floor on these are still TBF.
  • cgraceycgracey Posts: 11,129
    edited 2018-07-28 - 21:10:04
    To get a sample rate, just divide the clock frequency by power(2,n), where n = number of bits. At 180MHz:

    4 bits = 180_000_000/16 = 11.25MHz
    8 bits = 180_000_000/256 = 703KHz
    12 bits = 180_000_000/4096 = 43.9KHz

    The divisor needn't be a power of 2.
  • jmgjmg Posts: 13,520
    cgracey wrote: »
    To get a sample rate, just divide the clock frequency by power(2,n), where n = number of bits. At 180MHz:

    4 bits = 180_000_000/16 = 11.25MHz
    8 bits = 180_000_000/256 = 703KHz
    12 bits = 180_000_000/4096 = 43.9KHz

    The divisor needn't be a power of 2.

    Is there a sampling prescaler for the ADC integrator, or does it always run at SysCLK ?
    What are the integrator values ?
  • cgraceycgracey Posts: 11,129
    edited 2018-07-28 - 22:34:18
    It always runs at the system clock. The integrator is a 5uA current sink/source that continuously charges/discharges a 10pF cap.
  • OK, that is excellent news. Thanks to all.

    Mike R...
    The difference between theory and practice is that, in theory, there is no difference between theory and practice, but in practice, there is.
  • jmgjmg Posts: 13,520
    cgracey wrote: »
    It always runs at the system clock. The integrator is a 5uA current sink/source that continuously charges/discharges a 10pF cap.

    Thanks, that's 2us/V on the output, so be interesting to see how that runs at 160MHz - where that is then 3.125mV/SysCLK
  • cgraceycgracey Posts: 11,129
    edited 2018-07-29 - 00:37:30
    jmg wrote: »
    cgracey wrote: »
    It always runs at the system clock. The integrator is a 5uA current sink/source that continuously charges/discharges a 10pF cap.

    Thanks, that's 2us/V on the output, so be interesting to see how that runs at 160MHz - where that is then 3.125mV/SysCLK

    Right, it uses a chain of logic inverters from the 10pF integrator cap as a sense amplifier for speed and simplicity. The inverters' thresholds vary by process, but the current sources/sinks are very high impedance, so the exact integrator cap voltage doesn't matter.

    The current-steering scissor switches are built of thin-oxide PMOS and NMOS devices for biggest on/off delta. They switch signals around 1.65V, but their gates are driven at 0V or 3.3V, keeping them safe in a 3.3V environment. They switch the sink/source currents between the 10pF integrator cap and a smaller cap which is an active load, being a replica of the 10pF cap voltage. This keeps switching spikes down to 5mV, so the integrator voltage is not swayed much by charge injection.
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