Propeller II: Emulation of the P2 on FPGA boards (Prop123-A7/A9, DE0-NANO, DE2-115, etc)

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  • Hi Chip

    With the advent of bga package culture, there seems to be some misconcern about what happens underneath chip packages.

    Also Cmos logic have been long ago mentally associated with low power levels, hence lower dissipation. The farther many could think, is providing some top-bonded heat sink, to help spread high power levels.

    But limits have been pushed and we need to understand the present reality, almost doing a rescue of technics that have been of common use, from decades, mainly in the bipolar realm.

    Bottom exposed pad qfns and qfps does present some chalenges that, when properly addressed, let us fully realize the benefits of simultaneous electrical and thermal conduction thru a single element.

    Working with P2 have been, and sure will be, an entire electronics classroom by itself.
  • Yes, Enrique, I agree. OnSemi was interested to know what our recommended PCB design will be like, in terms of exposed-pad vias, ground planes, and dimensions. They intend to do a thorough heat dissipation analysis to make sure the chip works as intended in the likely setting.
  • YanomaniYanomani Posts: 702
    edited October 2017 Vote Up0Vote Down
    Hi Chip

    Maybe one of their concerns is the fact that P2 die area will closely match the maximum space available in the chosen package, hence it's using almost all the available exposed pad area.
    This implies that any gain in heat dissipation will be totally dependent of the design of the landing area underneath the chip.
    The three references I've posted earlier show how heat flow develops laterally, from the land pattern soldering area and its thermal vias, to any connected metal plane inside the multilayer board sandwich.
    The next one I'm just posting here, has an impressive image (page 15) of a cutoff made into a multilayer board, showing why removing extra metal surfaces inside the sandwich can lead to changes in the final PCB thickness, affecting its flatness and hence leaving an almost unnoticed very poor solder/contact interface, just under the chip.
    Please note that the same will apply to the vicinity of the heavily populated metal area, represented by the whole tqfp land pattern, in the several stacked planes.
    IMHO, judicious design of the whole chip setup, including the nearest smt components, can and will greatly influence the final result.

    Hope it helps

    Henrique

    https://smta.org/chapters/files/Heartland_Heartland_May_2015_BTC_DaleLee.pdf

    P.S.

    Another great resource from Ti, for the ones that simply love to do some math calculations. :lol:

    ti.com/lit/an/snva419c/snva419c.pdf
  • Would it be possible to run the P2 on the new Arduino Vidor 4000? It has a Cyclone 10 LP 10CL016 (16000 LE)
  • evanhevanh Posts: 5,952
    The FPGA used for emulating an 8 Cog Prop2 is a Cyclone V -A9 which has 300,000 LE. And is substantially used.

    Money is a placeholder for cooperation
  • evanhevanh Posts: 5,952
    edited June 4 Vote Up0Vote Down
    Actually, it can hold 16 Cogs but doesn't fit every thing else then. One Cog is maybe 13000 LE.

    Money is a placeholder for cooperation
  • 1 cog would be enough to start learning P2 ASM and Taqoz. With Arduino reputation, I expect that there will be much more owner than the DE0 nano
  • jmgjmg Posts: 12,640
    FredBlais wrote: »
    1 cog would be enough to start learning P2 ASM and Taqoz. With Arduino reputation, I expect that there will be much more owner than the DE0 nano

    Do you mean until P2 silicon arrives ? P2 Eval Boards would expect to be lower cost than an Arduino Vidor 4000, with more cores & more MHz & more RAM & all the analog. (so that 's not a wide time window.)

    I could see interest in P1V's on that platform - not sure if anyone has the MHz figures for a compile to Cyclone 10 LP 10CL016 ?
  • In fact, porting to the Vidor 4000 could be used as a marketing strategy : As I understand it, the FPGA hardware peripherals will be hosted on Arduino Create (web hosted IDE) a bit like objects in the OBEX. If we showcase the single core P2 there, we could gather some more interest towards the upcoming chip. Especially when the Vidor will be released this month there shouldn’t be a lot of others IP core to try so there’s no better timing than doing it ASAP. At least it’s worth the try...
  • evanhevanh Posts: 5,952
    edited June 4 Vote Up0Vote Down
    It's somewhere around 1500-1800 LE per Smartpin, so at best, only room for one Cog plus two Smartpins. That's not enough Smartpins at all. :(

    EDIT: DE-Nano has about 22000 LE and can only manage 8 Smartpins. See https://forums.parallax.com/discussion/162298/prop2-fpga-files-updated-2-june-2018-final-version-32i

    Doing a rough calc of the Nano it wouldn't fit with my above sizes. So 11000 per Cog and 1400 per Smartpin fits better.

    That would allow 3 Smartpins in the Vidor 4000. Still unusable.

    Money is a placeholder for cooperation
  • jmgjmg Posts: 12,640
    evanh wrote: »
    It's somewhere around 1500-1800 LE per Smartpin, so at best, only room for one Cog plus two Smartpins. That's not enough Smartpins at all. :(

    Valid point, what about a P1V and more smart pins then ?

    There seems good progress on compilers/spin that can run on both P1 and P2, so the focus here could be examples of Smart Pin use, where the code can compile for either a real P2, or the 'Vidor 4000 P2-'

    The Smart pins are a key point of difference of P2 (aside from the Analog, which no FPGA can emulate anyway)

    An unknown question here is how quickly will Vidor 4000 ramp ? As 'not yet released', it could have some shake-out passes to go yet ?
  • FredBlais wrote: »
    In fact, porting to the Vidor 4000 could be used as a marketing strategy : As I understand it, the FPGA hardware peripherals will be hosted on Arduino Create (web hosted IDE) a bit like objects in the OBEX. If we showcase the single core P2 there, we could gather some more interest towards the upcoming chip. Especially when the Vidor will be released this month there shouldn’t be a lot of others IP core to try so there’s no better timing than doing it ASAP. At least it’s worth the try...

    As a marketing strategy, this might make some sense Fred. You'd need to convince Chip to compile for a different family, and Chip's probably thinking his compiling days are finally over... and 16k is a fair bit less than the 22k~25k for current small fpga targets (no cordic)

    My conclusion on the Cyclone 10 LP was it was 'underwhelming' - similar MHz figures on P1V to Max10, but no flash onboard, and an $18 external configuration prom. The lattice parts are much more attractive for their size as Ariba points out. See this thread for all the details

    https://forums.parallax.com/discussion/166073/cyclone-10-early-info/p1
  • Can someone please point me to the schematics of the prop123-A9 boards? I shorted the board and believe I damaged a component in the power section... schematics might help me fix the board.
    Thanks
  • Yeah, it's not obvious where that was located now. Here's a copy of what I have stashed:
    Money is a placeholder for cooperation
  • Thank you @evanh !
  • Money is a placeholder for cooperation
  • evanhevanh Posts: 5,952
    edited November 20 Vote Up0Vote Down
  • An ideal cut down FPGA demo would have two cogs and at least one smart pin and preferably the CORDIC solver. That way someone could see what the P2 was all about. Most especially the multiple cogs. Without that, its just an oddball architecture that would leave people wondering why not use something more common. I dont think someone playing with a single cog would really be able to grasp what makes the P2 special. Of course, getting that to fit is a whole other issue and unfortunately probably isnt possible on the smaller devices.
    Particularly patient proactive practice positively predicates practically precise poly-processor Parallax Propeller programming paradigms.

    .
  • The reference for what will fit is here - https://forums.parallax.com/discussion/162298/prop2-fpga-files-updated-2-june-2018-final-version-32i/p1

    BeMicro-A2 is limited to one cog, 7 smartpins and no cordic. The A9's can almost fit everything. So, that's your useful range for gauging the minimum FPGA for your config.

    Money is a placeholder for cooperation
  • evanhevanh Posts: 5,952
    edited November 16 Vote Up0Vote Down
    Prototype die transistor count:
    cgracey wrote: »
    I estimate about 33M transistors, 27M of which are in the SRAMs, with the remaining 6M being logic. Within the I/O pins there are an additional ~400k transistors.

    https://forums.parallax.com/discussion/comment/1447668/#Comment_1447668

    Money is a placeholder for cooperation
  • FWIW ... it seems like the best way to introduce the multitudes of Arduino people to the P2 would be to design an Arduino board around the P2.

    Let's see... digital I/O: check. Analog: check. Multiple serial channels, check. Usb programmable, check. In fact, just about everything that Makers and educators might want in a controller, the P2 can do. If you don't bring out all of the I/o's ... so what? If you never use more than two or three Cogs so what? If you limit yourself to a setup and main loop and never use a fraction of the computing horsepower available... so what? It's a way of introducing thousands of users to the P2 and a few just might go on to actually learn about it's REAL abilities and design it into real products.

    I helped teach a robotics class to a group of home school kids a few years back. I tried to introduce the kids to the Propeller but it was the PARENTS who insisted on using the Arduino because of it's Maker community popularity. ( and a couple of dads who already felt comfortable with the boards) If I could have said: No problem, it IS an Arduino and you can program it with the same IDE, I might have brought this group into the Propeller community.

    If I knew anything about writing compilers ( which I unfortunately don't ) It seems like having a well documented C like language and an IDE with thousands ( tens of thousands?) of established users already comfortable with the IDE would be an incredibly tempting target for a new board, new software and new customers. Just sayin'.
  • evanhevanh Posts: 5,952
    edited December 5 Vote Up0Vote Down
    Does this count? https://www.parallax.com/product/32214

    EDIT: Looks like it's a good 6, maybe 7, years old.

    Money is a placeholder for cooperation
  • I think it was a good start evanh, however, as capable as the Propeller is, it doesn't have the memory or the language support that some of the much less expensive processors do. It is still an AMAZING control processor more capable in so many ways than most of the CPU's controlling the various Arduinos.

    However, the P1's main lack is the SOFTWARE behind what makes most Arduino users feel so comfortable: compatibility with the libraries, an IDE they know that works across a broad range of devices, etc.

    I have no doubt that the Propeller group COULD have hacked the P1 into being able to do many of these things, but it was never intended to be a "General Purpose" processor, and would take a lot of "shoe horning" to trick it into playing a role it was never intended for.

    The P2, on the other hand does have more "General Purpose" capabilities as well as enough internal memory to let it do most if not all of the things people want their Arduino's to do. This, combined with the incredible capabilities of the smart pins would make it a natural for a HUGE number of applications that makers and educators want to do: Robotics, CNC, intro programming training, etc.

    I'm probably barking up the wrong tree, but I think targeting a P2 for the Arduino tool set and libraries would introduce thousands of users out there to an incredible processor that they may never even HEAR of if it remains a separate entity.

    Once introduced, some of them may go on to learn about it's much more powerful capabilities when used with Spin(2) and assembly and become true "Propeller Heads".
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