Erroneous inter-Prop pull-down behavior
escher
Posts: 138
I'm splitting a workload between two P8Xs, using a single-wire simplex data transfer routine.
One cycle-shaving technique I'm using is loading outa at initialization and toggling dira to perform an ACK on the RX Propeller. This necessitates a pull-down resistor on the data line to ensure that the output responds appropriately to the high-impedance "floating" state the pins are in when they are set as inputs. I'm using a standard 10K resistor value for this purpose.
So the setup is:
The problem however that that the output is never going high, so no ACK.
@kuroneko and I discussed the issue and potential causes here.
Code in question:
Marko helped identify the problem as the frequency response, but I was wondering whether anyone had seen the same behavior or dealt directly with the same problem before. Thanks!
One cycle-shaving technique I'm using is loading outa at initialization and toggling dira to perform an ACK on the RX Propeller. This necessitates a pull-down resistor on the data line to ensure that the output responds appropriately to the high-impedance "floating" state the pins are in when they are set as inputs. I'm using a standard 10K resistor value for this purpose.
So the setup is:
Prop #1 P0 -> Prop #2 P0
|
v
10K -> Vss
The problem however that that the output is never going high, so no ACK.
@kuroneko and I discussed the issue and potential causes here.
Code in question:
or outa, RxPin ' Setup ACK output
rxbuff ' Send current buffer...
...
' Prepare for next buffer reception
or dira, RxPin ' Set RX pin as output for ACK
andn dira, RxPin ' Set RX pin as input
jmp #rxbuff ' Loop infinitely
Marko helped identify the problem as the frequency response, but I was wondering whether anyone had seen the same behavior or dealt directly with the same problem before. Thanks!
Comments
A short on the trace/line connecting the two Props.
Pin(s) damaged by having had both as outputs at some point.
Pin output is set to zero before entering "rxbuff".
Pin direction is changed to input before entering "rxbuff"
A 50nS high pulse is too short for the other prop to sense.
Start by verifying the pin is working by toggling it slowly.
-Phil
RxPin is defined as:
The link you gave has the answer already : ?
or outa, main ' mov outa, #0 ' 4 cycles mov dira, #0 ' 23 cycles (10K pull-down)ie the code is doing what you ask, it's just the time constant of the 10k and all the associated C's requires 23 sysclks before a LOW appears.
Since you appear to be chasing every last sysclk here, you could lower the 10k, or you could do what the 8051 has done for decades, and drive low briefly, then float.
ie enable OUT then disable to allow for any contention. This gives speed, but makes the R value far less critical, & is still 'wired or'.
The same technique works for the other-polarity, eg if you want to use RXD as a BUSY/ACK flag, that is pulled low on Byte-read, and goes hi when the RX side code is ready for another byte.
The 4 sysclk of hard drive, is gone quickly enough that the TX side has not driven the pin yet (and is likely waiting a start-bit time anyway...)
Place them (2 x 330R) in series and connect a 4k7R as a pull-down to VSS, at the point they are interconnected.
This way, each prop would see a ~5kR to VSS, plus any possible bias effect, comming from the other prop, thru the other 330R resistor.
Even if the inter-prop bias current is a reality, it'll be in the order of a few uA, althought it could yet be meassured by a good VOM, across of each resistor present at the setup.
Only my 0.02...
Henrique
In the last five decades, I can't remember pulling high or low any two I/O pins, of different ICs, meant to talk each other bidirectionally, without an interleaving series resistor, at least.
TTL, NMOS and CMOS domains already scanned, up to this moment.
To not being wrongly interpreted...
Usualy, dynamic currents flowing into each part power pins tend to generate slighly different biasing points for their input transistors.
Even at TTL logic leves and biasing currents, when dealing with high frequencies, actively pulling up or down was always better than doing it the passive way, specially when there are not a chance of having any series resistors, at all. Those ones among you all, that where used to deal with S-100 bus terminations would remember it, for sure.
At CMOS, those input transistors are particulary sensible, because of their natural high impedance, thus very low biasing currents.
Placing a single resistor between any two pins of different ICs, meant to be used as inputs, simultaneously, does not solve the problem, it only steps up the bias current level needed, to cause one input to adversely affect the biasing of the other (always remember, dynamic currents at play).
Two low-valued resistors in series, with a third one, at least an order or two of greater magnitude, meant to pull-up/pull-down the intersection node, always seemed to be a better aproach, at least to me.
Henrique
If you connect a scope at the pins the cap will even be much higher.
Andy
These are the details I was digging for, thank you!
Which is what your own link, and my post, already said....
I appreciate all the responses, but the specific details on the capacitance of the pins was the most critical to choosing a proper resistor value instead of guessing and checking. Re-reading my original question I notice I accidentally omitted that, sorry!
capacitances at full speed, so 1k or so is about right for a pull-up or pull-down.
For a serial connection at 115200 baud, 10k would be fine, but for fast logic 10k isn't reliable.
Exact margin depends on if both Props have the same SysCLK.
If you choose 3 as the target, a reduction from 23:3 indicates 1.3k, or you could drop a simple x10, to 1k, and get a 2.3 sysclk scaled delay.
An alternative to the suggested brief-high drive design (which saves the power wastage of low value pullups) is to add a WAIT line after you float.
That adds time, and pauses until whatever real RC is present, decays under that parts Vil threshold. An extra opcode delay adds a little margin so the other connected P1 can see that.
The assumption you're making is I'm familiar enough with electronics to make the extrapolation between high-impedance floating pin pull-down resistor shenanigans and arbitrary RC time constants and capacitance etc. etc. etc.
Not that difficult to calculate the resistor or time required once you know the capacitance. It takes 5 RC time constants to charge/discharge the capacitor in an RC circuit close to the applied voltage. The RC time constant is R x C, so in your case of 200pF that would be R x 200pF (or 200E-12pF). With a 1K resistor the time to charge that capacitor would be R x C x 5 or 1000 x 0.000_000_000_2 x 5 = 0.000_001 (1uSec).