Changing DE0-Nano P1 clock
escher
Posts: 138
I want to use 104 MHz as my P1 base clock ( @Heater. and @Cluso99 and others have extolled its stability) as my VGA display routine needs those sweet sweet nanoseconds.
I see in the top file for the DE0-Nano P1 the following declaration:
This is allegedly supposed to result in providing a 5 MHz input clock signal to the P1... but I don't see how as (50 MHz * 16)/5 = 160 MHz. So I'm stuck on even starting to figure out how to change these or other parameters to provide the propeller with a 6.5 MHz input clock signal (which with the 16x PLL would give me 104 MHz).
Anyone have experience with this? Thank you!
I see in the top file for the DE0-Nano P1 the following declaration:
pll : altpll with ( pll_type = "enhanced", operation_mode = "normal", inclk0_input_frequency = 20000, -- 20000ps = 50 MHz clk0_multiply_by = 16, clk0_divide_by = 5);
This is allegedly supposed to result in providing a 5 MHz input clock signal to the P1... but I don't see how as (50 MHz * 16)/5 = 160 MHz. So I'm stuck on even starting to figure out how to change these or other parameters to provide the propeller with a 6.5 MHz input clock signal (which with the 16x PLL would give me 104 MHz).
Anyone have experience with this? Thank you!
Comments
You could try these PLL mul/div values though to boost performance.
Edit: Actually Quartus allowed a multiply of 104 and a divide by 25 to generate 208 Mhz.
A test using _clkfreq = 104000000 and fullduplexserial @ 1Mbaud worked fine on a nano build.
This is based on a REAL P1V build for the DE0-Nano board.
I have run various code snippets on the board and at this point have found no issues.
In my experience with FPGA's, it's a lottery anyway.
I ran thru a lot of testing back in the days on the real P1, including 108MHz, as did a number of others. Saphieha did a lot of testing at 115MHz.
I wasn't aware any testing on P1V had been done above 80MHz. However, each FPGA compilation really needs the timing examined, and the verilog code just doesn't do it. Heck, we cannot even get a clean compile without Warnings.
What and where are these settings? I'm unfamiliar with them.
Getting crisp 640x480 @ 60 Hz video w/ a 104 MHz base clock:
Code here if interested
If you get a chance, push the clock frequency up until you start seeing issues, probably around 120 MHz