So a few weeks ago I had a chance to go to the Hackaday.com SuperConference in Pasadena CA, and I was one of the 40(?) lucky ones who did the FPGA workshop, by Sam Bobrowicz of Digilent Inc.
All the participants in the workshop got to take home an Arty FPGA board
, and a new Multi-Touch Display Shield with MicroSD adapter that is not available yet, as far as I can tell. The price for the workshop was probably about half of the value of this hardware. Thanks Digilent, Hackaday and sponsors!
The Arty is a great FPGA board for makers, with a Xilinx Artix-7 35T FPGA. It has 4 "PMOD" connectors with 8 signal pins each (PMOD is the standard that Digilent uses to make peripherals for this kind of board), and it also has a shield header for Arduino and ChipKit. There is Flash ROM on board and DDR3 RAM but unfortunately no I2C EEPROM.
As you may know, I've been maintaining the Propeller Hardware source code on Github (https://github.com/jacgoudsmit/P1V
) and I thought this would be an excellent opportunity to see if I could port the P1V sources to the Xilinx tools again. When @Mindrobots
were working on our initial Github repo of the Propeller HDL sources ("P8X32_Emulation"), we got some great submissions from Magnus Karlsson and others who ported the sources to the ISE tool that was in use for Xilinx targets back then. But this code hasn't been ported to the new "P1V" repo (which is the one that's based on the official Parallax Github release) until now.
Xilinx now has a new tool called Vivado, which (as I understand) integrates the steps of their development process better than the previous tools. I can't confirm that because I never used the older tools, but thanks to the Digilent workshop, I knew enough to be "dangerous" with Vivado. I imported the ISE project for the Pipistrello from the old P8X32_Emulation repo and it looks like it builds just fine but the source code is very different from the current HDL sources in the head revision of the Release branch of P1V, because we basically started over and Magnus made a lot of changes to the code to get everything to compile in ISE. So I haven't integrated Magnus' code into P1V just yet (there are other problems, for example the way he implemented hub memory is super straightforward but can't be used for the DE0-Nano because it doesn't have enough internal memory. But that's a whole different story).
I started a new Vivado project based on the current HDL sources in the head revision of my development branch, with the Arty as a target. It took me a day or so to figure out some minor problems which were basically me getting used to Vivado. For example, in the Altera (now Intel) Quartus software, I ignored pretty much all warnings, but I couldn't get Vivado to compile the source correctly without fixing all of them. Most warnings were caused by wires and regs being used before they were declared, apparently this is an important thing to get right in Vivado (I saw this afternoon that Chip has done some work recently in the P1V source code, to move some declarations around, so I guess he's aware of the problem too :-).
I eventually got the P1V source to compile for the Arty, but the bad news is that this FPGA is only big enough for 2 cogs.
The above is an image of the Artix-7 with a 2-cog P1V. The blue areas are the gates that are in use, and the green lines show how the I/O pins are connected. I guess I'm too spoiled with my Arrow BeMicroCV and BeMicroCV-A9 having plenty of space for the full Propeller with room to spare :-)
Anyway, I thought I'd share with you guys. This hasn't been checked in to my Github repo yet at this time; I need to do some housekeeping before I'll merge it, probably in the next few days. I'll keep you informed.
Thanks for reading!