Last night I was reading about NAND and NOR FLASH.
From what I read I believe OnSemi have both available. And articles suggest that there should be standard charge pumps for the erase cycle.
I had thought a small block of Flash would be nice so the P2 could boot a tiny program to do whatever was initially required. This could then load from flash, eeprom, SD card, or whatever. This could save having to use an external eeprom or flash Chip in some circumstances.
What I realised though, is that Flash is tiny compared to SRAM !!!
To be able to execute from it would require NOR FLASH.
There might be even be enough die space to have 512KB of HUB FLASH.
This could be a game changer!!!
Does NOR FLASH require an extra layer over what the P2 requires? Do I recall correctly that the smart pin ring required an extra layer??? Either way, it may be a small price to pay to get 1MB of hub.
I also noted that, as IIRC jmg said, OnSemi has not only an ONC180 (180nm), but now also an ONC110 (110nm) standard process. Are the costs prohibitive to move to 110nm. I understand the "outer ring has been done with 340nm??? Geometry. But isn't that just a 110/180nm process with larger features???
IMHO this shouldn't really delay the P2, other than the time to ask OnSemi and TreeHouse.