Friendly suggestions for parallax

Hey all,

I've been doing research on old 8 bit cpus lately, and I was reading on how simple chips, even with just say 16k transistors, used design teams of at least 5-10 people. And reading about processor design on my own, it's a miracle that chip has been able to make something a complex as the p1 all by himself. In retrospect it's awful that people on these forums have been literally demanding that chip make the p2 immediately like spoiled children.

Anyway, parallax, the propeller is your new flagship product. The basic stamp is no longer relevant today, the arduino is both cheaper and faster, but the prop is unique and has a unique niche in the market.

Maybe you should hire some more silicon designers parallax. Take the stress off of chip to make something as complex as a pentium all by himself. Bill mensch, the designer of the 6502, is still around and has his own company very similar to parallax where he still sells 6502 and 65186 SBCs. I would suggest contacting people like him and seeing if you could help take half the load off of chip.

And although chip has done the impossible already, what about the prop 3? Prop 4? Do you really expect him to make something even more complex than the p2 in the future, also all by himself? That's asking the impossible.

Comments

  • Actually, I'm hoping that P3 will be community-designed (actual written verilog, not just forum posts), with Chip taking the role of BDFL to ensure that the final product is deserving of the "Parallax Propeller" name.
  • Seairth wrote: »
    Actually, I'm hoping that P3 will be community-designed (actual written verilog, not just forum posts), with Chip taking the role of BDFL to ensure that the final product is deserving of the "Parallax Propeller" name.

    Huh... That's actually an amazing idea. Sort of like the Linux of CPUs.
  • jmgjmg Posts: 14,567
    m00tykins wrote: »
    I've been doing research on old 8 bit cpus lately, and I was reading on how simple chips, even with just say 16k transistors, used design teams of at least 5-10 people. And reading about processor design on my own, it's a miracle that chip has been able to make something a complex as the p1 all by himself. In retrospect it's awful that people on these forums have been literally demanding that chip make the p2 immediately like spoiled children.
    Even the P1 was not 'all by himself' and the P2 is rather less so.
    For P2, Chip is using tools written by Altera & FPGAs supplierd by Altera (not available to your old 8 bit designers), and he is using ASIC consultants and On Semi.

    P2 is about to enter a solid phase of Test Verification, and that will involve more than even those 5-10 you mention.

    Add-in the P2-eco system of Software tools, and the number grows again.
    Seairth wrote: »
    Actually, I'm hoping that P3 will be community-designed (actual written verilog, not just forum posts), with Chip taking the role of BDFL to ensure that the final product is deserving of the "Parallax Propeller" name.
    P2 is already close to community developed, and certainly the vital Test Verification phase is looking very much community driven.



  • P2 has been 10 years in the making so far so I don't think ANYONE has been literally DEMANDING that Chip make the P2 IMMEDIATELY like "spoiled children". So I find your
    "friendly" comment not so friendly as us forum friends have been encouraging Chip, contributing and testing, outlaying our time, money, and resources. I know I have. I just want Chip to make a P2 in silicon, not a P3 or P4 as it currently is in FPGA. Why? Because we are not just taking an academic interest in the project, we have commercial interest, and we have proven to be very very patient, and still interested. Very much unlike children.
  • Peter,
    There hasn't been much of late but there was a time or two in the past where quite a number of us were saying things like "It'll never be finished" and "The competition has/will left us behind" and "This has gone beyond the kitchen sink" and "I was counting on it being done by now".

    Those are demands in there own way. I'd guess that's the sort of comments m00tykins is talking about.
  • evanh wrote: »
    Peter,
    There hasn't been much of late but there was a time or two in the past where quite a number of us were saying things like "It'll never be finished" and "The competition has/will left us behind" and "This has gone beyond the kitchen sink" and "I was counting on it being done by now".

    Those are demands in there own way. I'd guess that's the sort of comments m00tykins is talking about.

    Uninformed and uncalled for comments I would say which is why I was not impressed.
  • Seairth wrote:
    Actually, I'm hoping that P3 will be community-designed ...
    With all due respect, I think we've already seen the downsides of that scheme. If anything, community involvement has slowed the development of the P2 and diluted any cohesive vision of what that chip should be.

    -Phil
  • Dave HeinDave Hein Posts: 6,264
    edited 2016-06-16 - 02:25:33
    m00tykins wrote: »
    In retrospect it's awful that people on these forums have been literally demanding that chip make the p2 immediately like spoiled children.
    I demand the P2 immediately!!! (or in the next decade or so -- it doesn't really matter when it comes out.)
    So if the P2 comes out in 2017, when would we expect the P3 -- 2027? And the P4 in 2037?
  • jmgjmg Posts: 14,567
    ... and diluted any cohesive vision of what that chip should be.

    Perhaps, but I have no idea what "diluted any cohesive vision" means - in practical terms, I know the first P2 conception did not include Smart Pins or USB support.
    Given those are in there, that is the opposite of what 'dilute' usually means ?

    The real test is not one of any perceived vision, but rather does the part have enough features to gain a critical mass is design-ins ?

    My instinct is, there is enough space between MCU and FPGA, for the P2 to do quite well.
    Given the trends for MCUs to morph into MPUs, P2 gets more useful.

  • Dave Hein wrote: »
    ... So if the P2 comes out in 2017, when would we expect the P3 -- 2027? And the P4 in 2037?
    Ah, there is certain to be more than one Prop2 variant. They must count, surely. :P
  • Prop2 is not a singular mask set, unlike the Prop1.
  • Lol, there's another one for ya, Peter - "... community involvement has slowed the development of the P2 and diluted any cohesive vision of what that chip should be."
  • jmgjmg Posts: 14,567
    evanh wrote: »
    Prop2 is not a singular mask set, unlike the Prop1.

    Prop2 is not yet any mask set at all .... :)

    It will have the ability to generate future variant mask sets, as demand & funding allow/dictate.

  • Seairth wrote:
    Actually, I'm hoping that P3 will be community-designed ...
    With all due respect, I think we've already seen the downsides of that scheme. If anything, community involvement has slowed the development of the P2 and diluted any cohesive vision of what that chip should be.

    You may be right. However, the cat's out of the bag, and I doubt you're going to put it back in. As you point out, the current approach has some drawbacks. So, where do you go from here?

    To me, there are at least two advantages to opening up the actual coding, compared to the current approach:
    1. With the source available, it's no longer good enough to just throw out neat ideas to the community. Anyone who argues in favor of one idea over another will be met with only one response: prove it. No need to argue theoretical differences, like we have been wont to do with the P2 design. Either you code it up and show everyone that it really is a great idea, or move on!
    2. When there are more than one reasonably good competing ideas (which was also the case with parts of the P2 design), we can actually test the alternatives. This differs from the current approach, where Chip can only reasonably implement one of the competing ideas at a time. There have been a number of rewrites of concepts in the P2 that could have been tested/demonstrated in parallel, if only more people were able to contribute code.

    Had both of these applied to the P2 design, it's conceivable that it would have taken less time to develop and ended up with a more coherent design. I'm not saying that it would have been a certainty, because none of us can know that (either way). But I definitely don't think the idea should be dismissed outright, just because the current approach didn't work well.
  • It was me. I have said things along the lines of:

    Get me it now!

    However, I'm also responsible for throwing one tiny, weeny, little extra feature suggestion into the pot that Chip implemented on the road to the failed "P2 Hot" design.

    Perhaps it's better we all shut up and let Chip get on with it.

    As for P3 and on. That will be a 64 bit, RISC-V, open source design, running Linux, with multiple Propeller style COGs and I/O system for the real time stuff.

    Yeah, OK, I fantasizing there.

  • I think the sausage will be good, after all the help from everyone over the last 10 years.
  • I live in a ex coal mining area and liked to stroll over the stuck piles, searching fossils. With the help of an microscope you can see so many details and discover, that ferns didn't change over 400 million years. But evolution took place always using the ressources available and there was no hope, just chances. So, 10 years is not a long time and the brain is an evolution accelerator, so the P2 evolved very quickly from the P1. And as we start to enumerate we find that P1 was originally P, only enumerated after P2 coming to existance and P3, P4, .. being discussed. I a short note Chip said, that he is reaching his limits. But those limits are only in the direction to do everything (more or less) alone, not in being able to supervice a next step of evolution. So I wish him a position of an Art Director, better P-Art-Director. Let us bring this P2 to an end (to the start) and develop great applications.
  • Did I hear.... SAUSAGE!!!!

    SO... does that mean the cogs are.... piglets
    AND... the Hub is... the trough
    AND... the Pins......trotters (smart of course)

    what else???

    Dave
  • Never ask what goes into sausage*, just enjoy the end results!!

    *product may contain up tp 10% digital byproducts and passive fillers
  • tritonium wrote: »
    Did I hear.... SAUSAGE!!!!

    SO... does that mean the cogs are.... piglets
    AND... the Hub is... the trough
    AND... the Pins......trotters (smart of course)

    what else???

    Dave

    A nursery rhyme for the modern age!

    This little piggy went to SPI.
    This little piggy stayed off.
    This little piggy had smart pins enabled.
    This little piggy had none.
    And this little piggy blinks an LED all day long!
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